3D atomic layer gate or junction extender

An apparatus comprising:

• a gated finned substrate comprising an isolation layer with a semiconductor fin formed thereon and a gate formed over the semiconductor fin;
• an atomic layer of dopant, consisting of a dopant material, formed on a portion of the semiconductor fin that is laterally adjacent to the gate;
• a lateral spacer formed on a sidewall of the gate and above a gate extension portion of the atomic layer of dopant;
• and
• a raised source or drain region formed on the semiconductor fin over the atomic layer of dopant laterally adjacent to the lateral spacer.

A method for fabricating a semiconductor device, the method comprising:

• receiving a gated finned substrate comprising an isolation layer with semiconductor fins formed thereon and gates formed over the semiconductor fins;
• masking off the gates and n-type regions of the semiconductor fins that are laterally adjacent to the gates and depositing, via atomic layer deposition, a p-type atomic layer of dopant on p-type regions of the semiconductor fins that are laterally adjacent to the gates;
• masking off the gates and p-type regions of the semiconductor fins that are laterally adjacent to the gates and depositing, via atomic layer deposition, an n-type atomic layer of dopant on n-type regions of the semiconductor fins that are laterally adjacent to the gates;
• forming lateral spacers on sidewalls of the gates and above gate extension regions of the atomic layer of dopant;
• and
• epitaxially growing, from the atomic layer of dopant, raised source and drain regions on the n-type regions and the p-type regions of the semiconductor fins.