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US 9,318,290 B2Granted
High voltage control with digital MEMS logic
AssigneeCiena Corporation
InventorMichael Y. Frankel
Life of this patent
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Abstract
A complex logic gate comprising digital MEM switches, coupled to a high voltage MEMS buffer, to provide a high voltage depending upon gate and body voltages of the digital MEM switches.
Claims20
An apparatus comprising:
- a Vdd voltage rail;
- a Vdd0 voltage rail;
- a reference rail;
- and
- a plurality of MEM (Micro-Electro-Mechanical) switch pairs, each pair comprising a first MEM switch and a second MEM switch, each first and second MEM switches in each pair comprising a first source/drain, a second source/drain, a gate, and a body;
- wherein all first MEM switches in the plurality of pairs are logically connected;
- wherein for each pair, the first source/drain of the first MEM switch is connected to the first source/drain of the second MEM switch;
- wherein the second source/drain of each second MEM switch is connected to the reference rail;
- wherein for a first subset of the pairs, the body of each first MEM switch in the first subset is connected to the reference rail and the body of each second MEM switch in the first subset is connected to the Vdd0 voltage rail;
- wherein a first pair in the plurality of pairs has the second source/drain of its first MEM switch connected to the Vdd voltage rail;
- and
- a MEMS (Micro-Electro-Mechanical System) buffer having an input port connected to a source/drain of the second MEM switch in a last pair of the plurality of pairs.
9 more elements
An apparatus comprising:
- a Vdd voltage rail;
- a Vdd0 voltage rail;
- a Vpull-in voltage rail;
- a reference rail;
- a plurality of buffers, each buffer comprising an input port and an output port, each buffer comprising MEM switches such that the output port is coupled to the Vpull-in voltage rail or to the reference rail depending upon whether the input port is coupled to the Vdd voltage rail or to the reference rail;
- a plurality of complex gates in one-to-one correspondence with the plurality of buffers, each complex gate comprising MEM switches, each MEM switch comprising a body and a gate;
- and
- an address decoder to provide a set of address voltages to the gates of each complex gate, wherein the bodies for each complex gate are connected to either the Vdd0 voltage rail or to the reference rail such that only one complex gate couples the input port of its corresponding buffer to the Vdd voltage rail depending upon the set of address voltages.
5 more elements
A method of controlling a micro-electro-mechanical (MEM) based relay using first, second and third address voltages bus signals, the method comprising:
- responsive to a configuration, coupling one or more of the first, second and third address voltages to associated digital MEM switches based on the configuration;
- and
- generating a control signal based on the coupled one or more of the first, second and third address voltages coupled to the associated digital MEM switches, wherein the associated digital MEM switches are connected in series and the control signal is provided to a high-voltage MEM buffer.
Dependencies are inferred from the claim text.