Hierarchical, distributed built-in self-repair solution

An integrated circuit comprising:

• one or more memory arrays, each memory array comprising one or more memory blocks;
• a built-in self-test (BIST) circuit configured to test one or more memory blocks in parallel;
• and
• one or more built-in soft-repair controllers (BISoR) configured to soft repair the memory blocks, wherein each built-in soft-repair controller is dedicated to a memory array, and wherein, each BISoR is simultaneously activated to soft repair one or more memory blocks which are being tested by the BIST circuit in parallel.

A method of testing on chip memory on an integrated circuit, comprising:

• configuring a first memory block of the one or more memory blocks in a memory array by a built-in self-test (BIST) circuit;
• testing a first memory block of the one or more memory blocks in a memory array by the built-in self-test (BIST) circuit;
• collecting information of failed memory locations during testing of the first memory block by a built-in soft-repair controller (BISoR);
• converting the information of failed memory locations into a soft repair data by the BISoR and storing the soft repair data in an internal memory of the BISoR;
• copying the soft repair data from the internal memory to the first memory block;
• and
• erasing the internal memory of the BISoR for soft repair of a second memory block of the one or more memory blocks, and wherein, the erasing of the internal memory is completed by the BISoR before the BIST circuit completes configuration of the second memory block for testing.

A method of testing on chip memory on an integrated circuit, comprising:

• configuring a first memory block in each of a plurality of memory arrays by a built-in self-test (BIST) circuit, wherein each memory array comprises one or more memory blocks;
• testing a first memory block in each of the plurality of memory arrays by a built-in self-test (BIST) circuit;
• collecting information of failed memory locations during testing of the first memory block in each of the plurality of memory arrays by a plurality of built-in soft-repair controllers (BISoR), wherein each BISoR of a plurality of BISoR is dedicated to a memory array;
• converting the information of failed memory locations into a soft repair data by the BISoR dedicated to each memory array and storing the soft repair data in an internal memory of the respective BISoR;
• copying the soft repair data from the internal memory of BISoR to the first memory block of the respective memory array;
• erasing the internal memory of the BISoR for soft repair of a second memory block in each of the plurality of memory arrays, and wherein, the erasing of the internal memory is completed by the respective BISoR before the BIST circuit completes configuration of the second memory block in each of the plurality of memory arrays for testing.