Data storage device and flash memory control method
AssigneeVIA Technologies, Inc.
InventorsChin-Yin Tsai, Yi-Lin Lai
Life of this patent
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Abstract
An overclocking process for a data storage device using a flash memory. A controller for the flash memory tests the flash memory using test clocks with various frequencies to determine at least one clock signal suitable to the flash memory. The clock candidates suitable to the flash memory are selected from the test clocks. The flash memory is operated in a variable-frequency manner by which the flash memory is switched between the clock candidates, such that electromagnetic interference is spread over different bands.
Claims16
A data storage device, comprising:
- a flash memory;
- and
- a controller coupled to the flash memory, wherein the controller tests the flash memory by a plurality of test clocks with various frequencies to determine at least one clock signal suitable to the flash memory and operates the flash memory in accordance with the clock signal suitable to the flash memory,
- wherein:
- the flash memory returns a response signal when the controller tests the flash memory by one of the test clocks;
- and
- the controller moves a sampling point, indicated by a test clock which is being tested, corresponding to the response signal when determining the clock signal suitable to the flash memory.
The data storage device as claimed in clam 1, wherein:
- a data transmission line is coupled between the controller and the flash memory;
- and
- the controller further switches the flash memory to operate at a single data rate for correct acquisition of data transmitted on the data transmission line.
A flash memory control method, comprising:
- testing a flash memory by a plurality of test clocks with various frequencies;
- determining a clock signal suitable to the flash memory based on testing the flash memory by the test clocks;
- operating the flash memory with the clock signal suitable to the flash memory;
- driving the flash memory to return a response signal when the flash memory is tested by one of the test clocks;
- and
- shifting the clock signal to move a sampling point corresponding to the response signal for determination of the clock signal suitable to the flash memory.
Dependencies are inferred from the claim text.