Digitally controlled source side select gate offset in 3D NAND memory erase

A monolithic three-dimensional non-volatile semiconductor memory device, comprising:

• a well structure formed in a silicon substrate;
• one or more strings each formed along a common channel structure above the well structure and running in a vertical direction relative to the substrate, each of the strings having a plurality of memory cells connected in series between the well structure and a corresponding bit line respectively through source side and drain side select gates, where the memory cells each have a charge storage medium and are arranged in multiple physical levels above the silicon substrate;
• and
• driver circuitry connected to receive a clock signal and connectable to apply voltage levels to the well structure and control gates of the memory cells, the source side select gates, and drain side select gates,
• wherein, when performing an erase operation on the strings, the driver circuitry applies to the well structure a first staircase waveform that begins with an initial level and increases in voltage with each of a first number of cycles of the clock signal and, after a delay of a second number of clock cycles subsequent to beginning to apply the first staircase waveform to the well structure, applies the first staircase waveform beginning with the initial level to the control gates of the source side select gates for the remainder of the first number of clock cycles.