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US 9,318,204 B1Granted
Non-volatile memory and method with adjusted timing for individual programming pulses
AssigneeSanDisk Technologies LLC
InventorsHan Chen, Man Lung Mui, Kou Tei
Life of this patent
Estimating the term…
Abstract
A non-volatile memory and method have programming circuitry that outputs a series of programming pulses of increasing voltage level to program in parallel a group of memory cells associated with a selected word line. Individual timing of the programming pulses such as rise and fall times of the pulse is optimally and dynamically adjusted according to the relative numbers of program-enabled and program-inhibited memory cells in the group associated with that pulse.
Claims20
A non-volatile memory, comprising:
- an array of memory cells;
- a plurality of word lines and bit lines for accessing the array of memory cells;
- and
- a programming circuit for programming a group of memory cells in parallel,
- the programming circuit comprising:
- word line driver circuitry for providing a programming voltage to a selected word line to the group of memory cells, the programming voltage comprising a series of pulses having increasing voltage levels;
- the group of memory cells having a number of program-enabled and program-inhibited memory cells that varies dynamically with each pulse of the series of pulses;
- and
- the word line driver circuitry including a control module to adjust an individual timing of a pulse of the series of pulses, responsive to relative numbers of program-enabled and program-inhibited memory cells in the group of memory cells associated with the pulse.
6 more elements
A method of operating a non-volatile memory, comprising:
- providing an array of memory cells;
- providing a plurality of word lines and bit lines for accessing the array of memory cells;
- and
- programming a group of memory cells in parallel,
- the programming comprising:
- applying a programming voltage to a selected word line to the group of memory cells, the programming voltage comprising a series of pulses having increasing voltage levels;
- determining a number of program-enabled and program-inhibited memory cells in the group of memory cells that varies dynamically with each pulse of the series of pulses;
- and
- adjusting an individual timing of a pulse of the series of pulses, responsive to relative numbers of program-enabled and program-inhibited memory cells in the group of memory cells associated with the pulse.
6 more elements
A non-volatile memory comprising:
- a 3D array of memory cells organized as a 2D array of vertical NAND strings across multiple memory planes above a substrate, with each memory cell of a NAND string residing in a different memory plane;
- a plurality of word lines and bit lines for accessing the array of memory cells;
- and
- a programming circuit for programming a group of memory cells in parallel,
- the programming circuit comprising:
- word line driver circuitry for providing a programming voltage to a selected word line to the group of memory cells, the programming voltage comprising a series of pulses having increasing voltage levels;
- the group of memory cells, having a number of program-enabled and a number of program-inhibited memory cells, that varies dynamically with each pulse of the series of pulses;
- and
- the word line driver circuitry comprising a control module to adjust an individual timing of a pulse of the series of pulses, responsive to relative numbers of program-enabled and program-inhibited memory cells in the group of memory cells associated with the pulse.
6 more elements
Dependencies are inferred from the claim text.