Semiconductor memory device including three-dimensional array structure
AssigneeSK hynix Inc.
InventorsJung Ryul Ahn, Yun Kyoung Lee
Life of this patent
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Abstract
A semiconductor memory device may include source selection transistors coupled to a common source line, source side dummy memory cells coupled between the source selection transistors and the normal memory cells, and drain selection transistors coupled to a bit line. The semiconductor memory device may include drain side dummy memory cells coupled between the drain selection transistors and the normal memory cells. A number of the source side dummy memory cells is less than a number of the drain side dummy memory cells, and a number of the drain selection transistors may be greater than the source selection transistors.
Claims20
A semiconductor memory device including normal memory cells stacked over a substrate, the semiconductor memory device comprising:
- source selection transistors coupled to a common source line;
- source side dummy memory cells coupled between the source selection transistors and the normal memory cells;
- drain selection transistors coupled to a bit line;
- and
- drain side dummy memory cells coupled between the drain selection transistors and the normal memory cells,
- wherein a number of the source side dummy memory cells is less than a number of the drain side dummy memory cells, and
- wherein a number of the drain selection transistors is greater than a number of the source selection transistors.
A semiconductor memory device, comprising:
- a pipe transistor;
- a first sub-cell string extending between the pipe transistor and a common source line and including source selection transistors coupled to the common source line and source side dummy memory cells coupled to the source selection transistors;
- and
- a second sub-cell string extending between the pipe transistor and a bit line and including drain selection transistors coupled to the bit line and drain side dummy memory cells coupled to the drain selection transistors,
- wherein a number of the source side dummy memory cells is less than a number of the drain side dummy memory cells, and a number of the drain selection transistors is greater than a number of the source selection transistors.
A semiconductor memory device including:
- a first sub-cell string stacked over a substrate and including a first set of normal memory cells;
- a second sub-cell string stacked over the substrate and including a second set of normal memory cells;
- drain selection transistors coupled to the second set of normal memory cells;
- and
- source selection transistors coupled to the first set of normal memory cells,
- wherein the first and second sub-cell strings are configured to reduce leakage current of the normal memory cells by including greater numbers of the drain selection transistors in the second sub-cell string than the source selection transistors in the first sub-cell string.
Dependencies are inferred from the claim text.