US 9,318,196 B1Granted

Non-volatile semiconductor memory device

AssigneeFloadia Corporation

InventorsHideo Kasai, Yutaka Shinagawa, Ryotaro Sakurai, Yasuhiro Taniguchi, Kosuke Okuyama

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Abstract

In a non-volatile semiconductor memory device capable of programming SRAM data in an SRAM into a non-volatile memory unit while implementing a high-speed operation in the SRAM, a voltage required to program the SRAM data into the non-volatile memory unit can be lowered. Thus, the SRAM can be operated at high speed with a low power supply voltage because the thickness of a gate insulating film of each of a first access transistor, a second access transistor, a first load transistor, a second load transistor, a first drive transistor, and a second drive transistor constituting the SRAM connected to the non-volatile memory unit can be set to 4 [nm] or less. Therefore, the SRAM data in the SRAM can be programmed into the non-volatile memory unit while a high-speed operation in the SRAM can be implemented.

A non-volatile semiconductor memory device comprising a non-volatile static random access memory (SRAM) memory cell including

an SRAM including a first load transistor and a first drive transistor having their respective one ends connected to each other, a first storage node being provided between the first load transistor and the first drive transistor, a second load transistor and a second drive transistor having their respective one ends connected to each other, a second storage node being provided between the second load transistor and the second drive transistor, a power supply line being connected to respective other ends of the first load transistor and the second load transistor, and a reference voltage line being connected to respective other ends of the first drive transistor and the second drive transistor, and
a non-volatile memory unit including a first memory cell having a first memory transistor and a first switch transistor connected in series with the first memory transistor in which a voltage is applied to one end of the first switch transistor from one of the first storage node and the second storage node and a second memory cell having a second memory transistor and a second switch transistor connected in series with the second memory transistor in which a voltage is applied to one end of the second switch transistor from the other one of the second storage node and the first storage node,
the SRAM further including
a first access transistor having one end connected to respective gates of the second load transistor and the second drive transistor and the first storage node, the other end connected to a complementary first bit line, and a gate connected to a word line, and
a second access transistor having one end connected to respective gates of the first load transistor and the first drive transistor and the second storage node, the other end connected to a complementary second bit line, and a gate connected to the word line, and
a thickness of a gate insulating film of each of the first access transistor, the second access transistor, the first load transistor, the second load transistor, the first drive transistor, and the second drive transistor is set to 4 [nm] or less.

3 more elements

Facts

Application

14/725,740Filed 29 May 2015

Granted

19 Apr 2016

Term ends

Not estimatedThe source records don’t support an estimate.

Classification6 codes

G11C 14/0063
In which the volatile element is a SRAM cell: and the nonvolatile element is an EEPROM element, e.g. a floating gate or MNOS transistor
G11C 5/025
Disposition of storage elements, e.g. in the form of a matrix array: geometric lay-out considerations of storage- and peripheral-blocks in a…
G11C 11/417
Auxiliary circuits, e.g. for addressing, decoding, driving, writing, sensing, timing or power reduction: for memory cells of the field-effect type
G11C 11/419
For memory cells of the field-effect type: read-write [R-W] circuits

Abstract

Claims15