Multi-level memory apparatus and data sensing method thereof
AssigneesSK hynix Inc., Korea Advanced Institute of Science and Technology
InventorsSeung Tak Ryu, Ji Wook Kwon, Dong Hwan Jin
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Abstract
A multi-level memory device may include a most significant bit (MSB) determination circuit configured to determine a plurality of MSBs by comparing a cell current flowing through a memory cell with a predetermined reference current, a current/voltage conversion circuit configured to convert a copied cell current obtained by copying the cell current into a cell voltage, a charging time determination circuit configured to determine a charging time during which the copied cell current is converted into the cell voltage and output a charging end signal, and a least significant bit (LSB) determination circuit configured to determine a plurality of LSBs according to the cell voltage and the charging end signal.
Claims17
A multi-level memory device comprising:
- a most significant bit (MSB) determination circuit configured to determine a plurality of MSBs by comparing a cell current flowing through a memory cell with a predetermined reference current;
- a current/voltage conversion circuit configured to convert a copied cell current obtained by copying the cell current into a cell voltage;
- a charging time determination circuit configured to determine a charging time during which the copied cell current is converted into the cell voltage and output a charging end signal;
- and
- a least significant bit (LSB) determination circuit configured to determine a plurality of LSBs according to the cell voltage and the charging end signal.
A multi-level memory device comprising:
- a plurality of analog/digital (A/D) converters;
- a charging time determination circuit configured to determine a time during which a copied cell current is converted into a cell voltage and output a charging end signal, the copied cell current being substantially the same as a cell current flowing through a memory cell;
- and
- a least significant bit (LSB) determination circuit configured to determine a plurality of LSBs of data stored in the memory cell according to the charging end signal,
- wherein the A/D converters share the charging time determination circuit and the LSB determination circuit.
A data sensing method of a multi-level memory device, comprising:
- determining a plurality of most significant bits (MSBs) by comparing a cell current flowing through a memory cell to a predetermined reference current;
- converting a copied cell current obtained by coping the cell current into a cell voltage, and storing the cell voltage during a charging time;
- determining the charging time during which the copied cell current is converted into the cell voltage and outputting a charging end signal;
- and
- determining a plurality of least significant bits (LSBs) according to the cell voltage and the charging end signal.
Dependencies are inferred from the claim text.