US 9,318,190 B1 · Memory device

Abstract

An electronic device is disclosed that includes n memory cells, a replica memory array, and a sensing unit. Each of the n memory cells stores bit data, in which n is a positive integer. The replica memory array includes a first reference memory cell having a high logic state, a second reference memory cell having a low logic state, n−1 first pseudo reference memory cells having the low logic state, and n−1 second pseudo reference memory cells having the high logic state. The first reference memory cell and the n−1 first pseudo reference memory cells generate a first signal, and the second reference memory cell and the n−1 second pseudo reference memory cells generate a second signal. The sensing unit determines a logic state of the bit data of one of the n memory cells according to the first signal and the second signal.

Claims22

Dependent claims

An electronic device, comprising:

n memory cells, each of the n memory cells being configured to store bit data, wherein n is a positive integer;
a replica memory array, comprising:
a first reference memory cell having a high logic state;
a second reference memory cell having a low logic state;
n−1 first pseudo reference memory cells having the low logic state;
and
n−1 second pseudo reference memory cells having the high logic state, wherein the first reference memory cell and the n−1 first pseudo reference memory cells are configured to generate a first signal, and the second reference memory cell and the n−1 second pseudo reference memory cells are configured to generate a second signal;
and
a sensing unit configured to determine a logic state of the bit data of one of the n memory cells according to the first signal and the second signal.

6 more elements

An electronic device, comprising:

a memory column, comprising n memory cells coupled to a data line, and n being a positive integer;
a replica memory array disposed at the side of the memory column, the replica memory array comprising:
a first reference memory cell having a high logic state;
a second reference memory cell having a low logic state;
n−1 first pseudo reference memory cells having the low logic state;
n−1 second pseudo reference memory cells having the high logic state;
a first reference line coupled to the first reference memory cell and the n−1 first pseudo reference memory cells;
and
a second reference line coupled to the second reference memory cell and the n−1 second pseudo reference memory cells;
and
a sense amplifier configured to read bit data of the n memory cells, wherein a first input terminal of the sense amplifier is coupled to the first reference line and the second reference line, and a second input terminal of the sense amplifier is coupled to the data line.

8 more elements

A method for controlling an electronic device, the electronic device comprising n memory cells, n being a positive integer, the method comprising:

generating a first signal by a first reference memory cell having a high logic state and n−1 first pseudo reference memory cells having a low logic state;
generating a second signal by a second reference memory cell having the low logic state and n−1 second pseudo reference memory cells having the high logic state;
and
determining a logic state of bit data of one of the n memory cells according to the first signal and the second signal by a sense amplifier.

1 more element

Dependencies are inferred from the claim text.

Memory device

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Memory device

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Abstract

Claims22