Memory module and memory system including the same

A memory system comprising:

• a memory module;
• and
• a memory controller configured to output an address and a command to the memory module,
• wherein the memory module includes:
• first through N-th memory devices, each of the first through N-th memory devices being divided into first through M-th regions, each of the first through N-th memory devices including a max-count address generator,
• wherein for each of the max-count address generators, the max-count address generator is configured to count a number of accesses to a row address included in respective J-th regions of the first through N-th memory devices and is configured to output a max-count address information when the number of the counted accesses reaches a threshold value, where M and N are integers equal to or greater than 2, and J is a natural number equal to or less than M;
• and
• a buffer unit configured to receive the max-count address information from the first through N-th memory devices and configured to output a target row address to refresh memory cells of the target row address of the first to N-th memory devices corresponding to the max-count address information,
• wherein each of the max-count address generators is configured to count a number of accesses for a set of row addresses different from the sets of row addresses for which the other max-count address generators count accesses.

A memory module comprising:

• m memory devices, each of the m memory devices being divided into n regions each region including a plurality of rows corresponding to row addresses, where m and n are integers equal to or greater than 2;
• and
• an address detector included in each of the m memory devices, wherein for each of the address detectors, the address detector is configured to count a number of accesses to a particular row address included in one region of each of the m memory devices during a predetermined time period, and is configured to output a detect signal when the number of the counted accesses reaches a reference value,
• wherein each of the address detectors is configured to count a number of accesses for a set of row addresses different from the sets of row addresses for which the other address detectors count accesses.