Maintenance operations in a DRAM

A memory device comprising:

• a plurality of memory banks, each bank including a plurality of rows of memory cells;
• a command interface operable to accept commands from a memory controller;
• refresh circuitry configured to perform a self-refresh operation to refresh data stored in at least one bank of the plurality of memory banks in response to a self-refresh command from the memory controller;
• and
• control logic to configure the enable the command interface to enter a calibration mode while the refresh circuitry performs the self-refresh operation;
• wherein
• in the calibration mode, the command interface is configured to perform a respective calibration operation, of a plurality of calibration operations, in accordance with an operation code received from the memory controller.

A memory device comprising:

• a plurality of memory banks, each bank including a plurality of rows of memory cells;
• interface means for accepting commands from a memory controller;
• refresh means configured to perform a self-refresh operation to refresh data stored in at least one bank of the plurality of memory banks in response to a self-refresh command from the memory controller;
• and
• logic means to configure the enable the command interface to enter a calibration mode while the refresh circuitry performs the self-refresh operation;
• wherein
• in the calibration mode, the interface means is configured to perform a respective calibration operation, of a plurality of calibration operations, in accordance with an operation code received from the memory controller.