Apparatus, method and system to determine memory access command timing based on error detection
AssigneeIntel Corporation
InventorJohn V. Lovelace
Life of this patent
Estimating the term…
Abstract
Techniques and mechanisms to dynamically adjustment a timing of commands to access a dynamic random access memory (DRAM). In an embodiment, a memory controller monitors an error rate of the DRAM and, based on such monitoring, identifies that the error rate is within a predetermined range. In response to the error rate being within the predetermined range, one or more signals are generated to dynamically modify a command timing setting. In another embodiment, modification of the command timing setting is to transition a memory controller from sending memory refresh commands successively at one rate to sending memory refresh commands successively at a different rate.
Claims25
A memory controller comprising:
- command logic to generate first commands to access a dynamic random access memory (DRAM) coupled to the memory controller, including the command logic to generate the first commands according to a first timing;
- and
- detect logic to monitor an error rate of the DRAM and to send to a basic input output system (BIOS) an indication of the error rate, wherein based on the indication, the BIOS to identify that the error rate is within a predetermined range and generates one or more signals in response to the error rate being within the predetermined range, the one or more signals to dynamically modify a command timing setting to transition from the first timing to a second timing, wherein, based on the one or more signals, the command logic to generate second commands according to the second timing, the second commands to access the DRAM.
A method at a memory controller, the method comprising:
- generating first commands to access a dynamic random access memory (DRAM) coupled to the memory controller, including generating the first commands according to a first timing;
- monitoring an error rate of a dynamic random access memory (DRAM) during runtime operation of the DRAM;
- and
- based on the monitoring, sending from the memory controller to a basic input output system (BIOS) an indication that the error rate is within a predetermined range, generating at, wherein, in response to the indication, the BIOS generates one or more signals to dynamically modify a command timing setting to transition from a first timing for first commands to access the DRAM to a second timing for second commands to access the DRAM.
A computer-readable storage medium having stored thereon instructions which, when executed by one or more processing units, cause the one or more processing units to perform a method at a memory controller, the method comprising:
- generating first commands to access a dynamic random access memory (DRAM) coupled to the memory controller, including generating the first commands according to a first timing;
- monitoring an error rate of a dynamic random access memory (DRAM) during runtime operation of the DRAM;
- and
- based on the monitoring, sending from the memory controller to a basic input output system (BIOS) that the error rate is within a predetermined range, wherein, in response to the indication, the BIOS generates one or more signals to dynamically modify a command timing setting to transition from a first timing for first commands to access the DRAM to a second timing for second commands to access the DRAM.
A system comprising:
- a dynamic random access memory (DRAM);
- a command-address bus;
- and
- a memory controller coupled to the DRAM via the command-address bus, the memory controller including:
- command logic to generate first commands to access the DRAM, including the command logic to generate the first commands according to a first timing;
- and
- detect logic to monitor an error rate of the DRAM and to send to a basic input output system (BIOS) an indication of the error rate, wherein based on the indication, the BIOS to identify that the error rate is within a predetermined range and generates one or more signals in response to the error rate being within the predetermined range, the one or more signals to dynamically modify a command timing setting to transition from the first timing to a second timing, wherein, based on the one or more signals, the command logic to generate second commands according to the second timing, the second commands to access the DRAM.
Dependencies are inferred from the claim text.