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US 9,318,180 B2Granted
MRAM wtih metal gate write conductors
AssigneeIII Holdings 1, LLC
InventorKrishnakumar Mani
Life of this patent
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Abstract
In one embodiment of the invention, there is provided a magnetic random access (MRAM) device. The device comprises a plurality of MRAM cells, wherein each MRAM cell comprises a magnetic bit, and write conductors defined by conductors patterned in a second metal layer above the magnetic bit; and a gate formed below the magnetic bit between a source and a drain; and addressing circuits to address the MRAM cells.
Claims11
A magnetic random access memory (MRAM) cell, comprising:
- a source and a drain formed in a substrate;
- a read/write gate electrode formed on the substrate between the source and drain and configured to operate as both a read word line electrode and a write word line electrode;
- a drain contact stud connected to the drain;
- a source lead connected to the source;
- a read metal lead of a read metal layer formed above the read/write gate electrode, drain contact, and source lead, wherein the read metal lead couples the drain contact stud to the read/write gate electrode;
- a magnetic bit formed on the read metal lead and above the read/write gate electrode;
- and
- a write conductor of a write metal layer formed above the magnetic bit, wherein the write conductor is coupled to the magnetic bit.
5 more elements
A magnetic random access memory (MRAM) device, comprising:
- a first global write word line;
- a second global write word line;
- a plurality of first local write word lines coupled to the first global write word line;
- and
- a plurality of second local write word lines coupled to the second global write word line;
- wherein each local write word line of the first and second local write word lines has a corresponding plurality of magnetic bits;
- wherein each magnetic bit of the plurality of magnetic bits comprises an associated read line and an associated bit line;
- wherein each magnetic bit comprises a Magnetic Tunnel Junction (MTJ) stack;
- and
- wherein each MTJ stack has an associated write transistor and an associated read transistor.
7 more elements
Dependencies are inferred from the claim text.