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US 9,318,178 B2Granted
Semiconductor storage device and data processing method
AssigneeHitachi, Ltd.
InventorsTakayuki Kawahara, Riichiro Takemura, Kazuo Ono, Nobuaki Kohinata
Life of this patent
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Abstract
Since a nonvolatile RAM allows random reading and writing operations, an erasing mode is unnecessary. From the system side, however, it is desirable to have the erasing mode because of its nonvolatile characteristic. Moreover, the erasing operation is desirably carried out at high speed with low power consumption. Therefore, memory cell arrays COA and DTA containing a plurality of memory cells MC each having a magnetoresistive element are provided, a series of data is written to the memory cell arrays COA and DTA, and at the time of erasing, an erasing operation is carried out by writing predetermined data only to the memory cell array COA.
Claims21
A semiconductor storage device comprising:
- a memory cell array having a plurality of word lines, a plurality of bit lines which intersect with the plurality of word lines, and a plurality of memory cells disposed at predetermined intersections between the plurality of word lines and the plurality of bit lines;
- and
- a command control circuit which controls writing and reading operations to and from the memory cell array,
- wherein each of the plurality of memory cells includes:
- a tunnel magnetoresistive element having a tunnel film, a pinned layer which is placed adjacent to the tunnel film and whose electron spin direction is fixed to a predetermined direction, and a free layer which is placed adjacent to a surface of the tunnel film which is opposed to the surface adjacent to the pinned layer and whose electron spin direction is set either in parallel with or in anti-parallel with the pinned layer;
- and
- a MOSFET whose gate is connected to the word line and whose drain is connected to the pinned layer side of the tunnel magnetoresistive element, and
- wherein when the command control circuit receives a writing command containing an address signal which indicates to which memory cells among the plurality of memory cells a writing operation is to be carried out, the command control circuit writes a series of data, which serves as one unit and is externally input, to the memory cells indicated by the address signal, and
- the series of data written in accordance with the writing command is brought into an erased state by writing predetermined data to only a part of memory cells to which the series of data has been written, such that when a reading operation is then carried out only meaningless data rows are read, whereby high security can be achieved.
6 more elements
A semiconductor storage device comprising:
- a memory cell array having a plurality of word lines, a plurality of bit lines which intersect with the plurality of word lines, and a plurality of first and second memory cells disposed at predetermined intersections between the plurality of word lines and the plurality of bit lines;
- a dummy data pattern block;
- a selection circuit which selects data output from the memory cell array and data output from the dummy data pattern block;
- and
- a command control circuit which controls writing and reading operations to and from the memory cell array,
- wherein each of the plurality of second memory cells includes:
- a tunnel magnetoresistive element having a tunnel film, a pinned layer which is placed adjacent to the tunnel film and whose electron spin direction is fixed to a predetermined direction, and a free layer which is placed adjacent to a surface of the tunnel film which is opposed to the surface adjacent to the pinned layer and whose electron spin direction is set either in parallel with or in anti-parallel with the pinned layer;
- and
- a MOSFET whose gate is connected to the word line and whose drain is connected to the pinned layer side of the tunnel magnetoresistive element,
- wherein each of the plurality of first memory cells retains information indicating that a corresponding one of the plurality of second memory cells is in a writing state or information indicating that the corresponding one of the plurality of second memory cells is in an erasing state, and
- wherein when the command control circuit receives a reading command containing an address signal which indicates from which memory cells among the plurality of second memory cells the data is to be read, if the information retained by the first memory cell corresponding to the address signal among the plurality of first memory cells indicates the writing state, the selection circuit selects the data output from the plurality of second memory cells, and if the information retained by the first memory cell corresponding to the address signal among the plurality of first memory cells indicates the erasing state, the selection circuit selects the data output from the dummy pattern data block.
8 more elements
A semiconductor storage device comprising:
- a memory cell array having a plurality of word lines, a plurality of bit lines which intersect with the plurality of word lines, and a plurality of first and second memory cells disposed at predetermined intersections between the plurality of word lines and the plurality of bit lines;
- and
- a command control circuit which controls writing and reading operations to and from the memory cell array,
- wherein each of the plurality of first memory cells includes:
- a tunnel magnetoresistive element having a tunnel film, a pinned layer which is placed adjacent to the tunnel film and whose electron spin direction is fixed to a predetermined direction, and a free layer which is placed adjacent to a surface of the tunnel film which is opposed to the surface adjacent to the pinned layer and whose electron spin direction is set either in parallel with or in anti-parallel with the pinned layer;
- and
- a MOSFET whose gate is connected to the word line and whose drain is connected to the pinned layer side of the tunnel magnetoresistive element,
- wherein the first memory cells and the second memory cells are different types of memory cells so that each of the plurality of first memory cells has an information retention period which is longer than an information retention period of each of the plurality of second memory cells, and
- wherein when the command control circuit receives a writing command containing an address signal which indicates to which memory cells among the plurality of first memory cells and/or second memory cells a writing operation is to be carried out, the command control circuit writes data input from outside to the first memory cells and the second memory cells indicated by the address signal in a divided manner among the plurality of first memory cells and the plurality of second memory cells.
6 more elements
Dependencies are inferred from the claim text.