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US 9,318,174 B1Granted
Memory systems and methods involving high speed local address circuitry
AssigneeGSI Technology, Inc.
InventorsPatrick Chuang, Mu-Hsiang Huang, Lee-Lean Shu
Life of this patent
Estimating the term…
Abstract
Systems and methods of memory and memory operation are disclosed, such as providing a circuit including a local address driver voltage source for memory decoding. In one exemplary implementation, an illustrative circuit may comprise a first buffer and a capacitor. The first buffer may comprise a power input and a ground input. The capacitor may comprise a first terminal connected to the power input of the first buffer and a second terminal connected to the ground input of the first buffer. When the first buffer draws a current from the power input, at least a portion of the current may be supplied by the capacitor.
Claims24
A circuit comprising:
- a first complementary buffer comprising a power input and a ground input;
- a capacitor comprising a first terminal connected to the power input of the first buffer and a second terminal connected to the ground input of the first buffer so that when the first buffer draws a current from the power input, at least a portion of the current is supplied by the capacitor from the first terminal;
- a second complementary buffer comprising a power input, a ground input, and a line input;
- and
- an inverter connected to the line input of the second buffer;
- wherein the first terminal of the capacitor is also connected to the power input of the second buffer and the second terminal of the capacitor is also connected to the ground input of the second buffer such that, via coupling of the power input to the second buffer that draws a current supply, a current is supplied from the ground input of the second buffer to the second terminal of the capacitor;
- and
- wherein via electrical coupling of the current supplied to the second terminal of the capacitor from the ground input of the second buffer and the current supplied to the first buffer from the first terminal of the capacitor, the capacitor is cyclically charged and discharged to recycle current between the first buffer and the second buffer.
5 more elements
A circuit comprising:
- a first complementary buffer configured to deliver a first data signal to a memory circuit;
- and
- a capacitor coupled to the first buffer so that when the first buffer draws a current from a power source, at least a portion of the current is supplied by the capacitor;
- a second complementary buffer configured to deliver a second data signal to the memory circuit;
- and
- an inverter coupled to the second buffer configured to supply the second data signal to the second buffer;
- wherein the capacitor is also coupled to the second buffer such that, via coupling of the power input to the second buffer that draws a current supply, a current is supplied from the second buffer to the capacitor;
- and
- wherein via electrical coupling of the current supplied to the capacitor from the second buffer and the current supplied to the first buffer from the capacitor, the capacitor is cyclically charged and discharged to recycle current between the first buffer and the second buffer.
6 more elements
A method of operating a circuit comprising:
- receiving a first data signal at a line input of a first complementary buffer of a memory address circuit;
- drawing a current, with the first buffer, when the first data signal is received at the line input of the first buffer, wherein at least a portion of the current drawn by the first buffer is supplied by a capacitor coupled to the first buffer via a first terminal of the capacitor;
- receiving a second data signal at an inverter of the memory address circuit;
- outputting, with the inverter, an inverted second data signal to a line input of a second complementary buffer of the memory address circuit;
- drawing a current, via the second buffer, when the inverted second data signal is received at the line input of the second buffer;
- and
- supplying a current, via the second buffer, to a second terminal of the capacitor when the inverted second data signal is received at the line input of the second buffer;
- wherein via the current supplied to the second terminal of the capacitor from the second buffer and the current supplied to the first buffer from the first terminal of the capacitor, the capacitor is cyclically charged and discharged to recycle current between the first buffer and the second buffer.
5 more elements
Dependencies are inferred from the claim text.