US 9,318,171 B2 · Dual asynchronous and synchronous memory system

Abstract

A computer-system implemented method for dual asynchronous and synchronous memory operation in a memory subsystem includes establishing a synchronous channel between a memory controller and a memory buffer chip. A mode selector determines a reference clock source for a memory domain phase-locked loop of the memory buffer chip based on an operating mode of the memory buffer chip. An output of a nest domain phase-locked loop is provided as the reference clock source to the memory domain phase-locked loop in the memory buffer chip based on the operating mode being synchronous. The nest domain phase-locked loop is operable synchronous to a memory controller phase-locked loop of the memory controller. A separate reference clock is provided independent of the nest domain phase-locked loop as the reference clock to the memory domain phase-locked loop based on the operating mode being asynchronous.

Claims12

Dependent claims

A computer system implemented method for dual asynchronous and synchronous memory operation in a memory subsystem, the method comprising:

establishing a synchronous channel between a memory controller and a memory buffer chip;
determining, by a mode selector, a reference clock source for a memory domain phase-locked loop of the memory buffer chip based on an operating mode of the memory buffer chip;
providing an output of a nest domain phase-locked loop as the reference clock source to the memory domain phase-locked loop in the memory buffer chip based on the operating mode being synchronous, the nest domain phase-locked loop operable synchronous to a memory controller phase-locked loop of the memory controller;
and
providing a separate reference clock independent of the nest domain phase-locked loop as the reference clock to the memory domain phase-locked loop based on the operating mode being asynchronous.

2 more elements

A computer program product for synchronizing a dual asynchronous and synchronous memory subsystem, the computer program product comprising:

a non-transitory storage medium readable by a processing circuit and storing instructions for execution by the processing circuit for performing a method comprising:
initializing and calibrating lanes of a synchronous channel by a memory controller coupled to a memory buffer chip via the synchronous channel;
calculating a frame round trip latency for the synchronous channel by the memory controller;
establishing a frame transmission protocol based on the calculated frame round trip latency;
and
establishing a synchronization reference for the memory buffer chip by the memory controller, the memory buffer chip including a synchronous operating mode and an asynchronous operating mode relative to the memory controller.

3 more elements

Dependencies are inferred from the claim text.

Dual asynchronous and synchronous memory system

Life of this patent

Dual asynchronous and synchronous memory system

Life of this patent

Abstract

Claims12