Storage device, memory cell, and data writing method

A memory cell included in a storage device comprising:

• a memory cell comprising a first storage circuit with a write time t1 and a data retention time τ1 and a second storage circuit with a write time t2 and a data retention time τ2 (t1<t2 and τ1<τ2), wherein a data storage node of the first storage circuit and a data storage node of the second storage circuit are connected each other;
• a power control circuit for controlling supply of power to the memory cell;
• and a write data supply circuit for supplying write data to the memory cell,
• wherein the write data supply circuit supplies write data to the memory cell to write the data on the first storage circuit over a write time tW that is longer than the write time t1 which is a time necessary for writing data on the first storage circuit and that is shorter than the write time t2 which is a time necessary for writing data on the second storage circuit, and stops the supply of the write data at conclusion of the elapsed write time tW;
• and
• the power control circuit supplies power to the memory cell over a time that is longer than the write time t2 of the second storage circuit when the write data is supplied from the write data supply circuit to the memory cell, writes, on the second storage circuit, the data written on the first storage circuit once the supply of the write data is stopped, and stops the supply of the power to the memory cell after a lapse of the write time t2 of the second storage circuit following start of the supply of the write data.

A data writing method comprising writing data on a plurality of memory cells comprising a first storage circuit with a write time t1 and a data retention time τ1and a second storage circuit with a write time t2 and a data retention time τ2 (t1<t2 and τ1<τ2), wherein

• a memory cell targeted for writing is selected to start supplying power to the memory cell;
• concurrently, data is written on the first storage circuit and the second storage circuit in parallel over a write time tW that is longer than the write time t1 which is a time necessary for writing data on the first storage circuit and that is shorter than the write time t2 which is a time necessary for writing data on the second storage circuit;
• and
• the selection of the memory cell is finished after the elapse of time tW following start of the writing of the data, the data written on the first storage circuit is written on the second storage circuit, and the supply of the power to the memory cell is stopped after a lapse of the write time t2 of the second storage circuit following the start of the supply of the write data.