Bit line equalizing circuit

A bit line equalizing circuit comprising:

• an active region traversed by a first bit line and a second bit line;
• a plurality of transistors serially connected between the first bit line and the second bit line, and configured to supply a predetermined voltage to the first bit line and the second bit line;
• and
• an equalizing transistor connected between the first bit line and the second bit line, and configured to equalize a voltage of the first bit line and a voltage of the second bit line,
• wherein the plurality of transistors and the equalizing transistor share a gate pattern,
• wherein the gate pattern includes a first pattern disposed on the active region in a first direction, and a second pattern extended from one side of the first pattern to be disposed in a second direction crossing the first direction, and
• wherein the second pattern is bent at a first position in the first direction, and bent at a second position different from the first position in the second direction to be extended, the first position and the second position being included in the active region.

A bit line equalizing circuit comprising:

• an equalizing transistor which is connected to a first bit line and a second bit line, and configured to be turned on if an equalizing signal is input;
• and
• a plurality of transistors which are connected to one another, configured to be turned on and provide a predetermined voltage to the first and second bit lines, if the equalizing signal is input,
• wherein the first and second bit lines are equalized to have a same voltage by the predetermined voltage,
• wherein the plurality of transistors and the equalizing transistor share a gate pattern, and
• wherein the gate pattern includes a first pattern disposed on an active region in a first direction, and a second pattern extended from one side of the first pattern to be disposed in a second direction crossing the first direction, the second pattern being formed in a stair shape on the active region.