Information processing apparatus

An information processing apparatus comprising:

• a plurality of cores;
• a shared resource that can be shared by the plurality of cores;
• and
• a local register that stores configuration information peculiar to each of the plurality of cores, wherein
• the shared resource is provided independently from the plurality of cores, and
• the local register is provided to each of the plurality of cores,
• wherein the shared resource includes a memory protection unit that protects a shared memory from invalid access by each of the plurality of cores,
• wherein each of the plurality of cores further comprises a local memory protection unit that evaluates whether or not the corresponding core can access the shared memory prior to evaluation by the memory protection unit,
• wherein the local memory protection unit comprises:
• a second protected area configuration register that stores protected area information relating to a protected area of the shared memory;
• and
• a second access evaluation circuit that is provided to correspond to the second protected area configuration register and evaluates whether or not the corresponding core is allowed to access the shared memory based on the memory access information and the protected area information stored to the second protected area configuration register,
• wherein the memory protection unit comprises:
• a first protected area configuration register that stores protected area information relating to a protected area of the shared memory;
• and
• an area evaluation circuit that evaluates, when the memory address included in the memory access information is not included in a memory area stored to the second protected area configuration register, whether or not the memory address is included in the memory area stored to the first protected area configuration register,
• wherein
• the local memory protection unit further comprises a rewrite control circuit that rewrites, when the area evaluation circuit evaluates that the memory address is included in the memory area stored to the first protected area configuration register, protected area information stored to the second protected area configuration register using protected area information stored to the first protected area configuration register, and
• after the second protected area configuration register is rewritten, the second access evaluation circuit evaluates again whether or not the core is allowed to access the shared memory based on the memory access information and rewritten protected area information stored to the second protected area configuration register.