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US 9,318,164 B2Granted
Semiconductor memory device with power-saving signal
AssigneeSK hynix Inc.
InventorHyun Chul Lee
Life of this patent
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Abstract
A semiconductor memory device includes a memory cell array, a voltage generator suitable for generating voltages used for controlling the memory cell array in response to a power-saving signal, and a control logic suitable for providing a power-saving signal to the voltage generator, based on a chip select signal. The control logic includes a delay block suitable for delaying the chip select signal and generating the power-saving signal based on the delayed chip select signal.
Claims18
A semiconductor memory device comprising:
- a memory cell array;
- a voltage generator suitable for generating voltages used for accessing the memory cell array in response to a power-saving signal;
- and
- a control logic suitable for generating the power-saving signal that is activated when the chip select signal retains a deactivated state for a reference period or longer after an entry of a power-saving mode,
- wherein the control logic comprises:
- a first delay block suitable for generating a first delayed signal by delaying an edge of the chip select signal by a first delay time;
- a second delay block suitable for determining whether the first delayed signal is deactivated for the reference period or more, and generating a second delayed signal based on the determination result;
- and
- a third delay block suitable for generating the power-saving signal by delaying an edge of the second delayed signal by a third delay time, which is equal to or longer than the second delay time.
6 more elements
A semiconductor memory device comprising:
- a memory cell array;
- a voltage generator suitable for generating voltages used for controlling the memory cell array in response to a power-saving signal;
- and
- a control logic suitable for providing the power-saving signal to the voltage generator, based on a chip select signal,
- wherein the control logic includes a delay block suitable for delaying the chip select signal and generating the power-saving signal based on the delayed chip select signal,
- wherein the delay block comprises:
- a first delay block suitable for generating a first delayed signal by delaying the chip select signal by a first delay time;
- a second delay block suitable for determining whether or not the first delayed signal is deactivated for a time longer than a second delay time, and generating a second delayed signal based on the determination result;
- and
- a third delay block suitable for generating the power-saving signal by delaying the second delayed signal by a third delay time,
- wherein the third delay block generates the power-saving signal by delaying the second delayed signal by the third delay time equal to or longer than the second delay time.
8 more elements
A data storage device comprising:
- a semiconductor memory device;
- and
- a controller suitable for accessing the semiconductor memory device in response to a request from a host device,
- wherein the semiconductor memory device comprises:
- a memory cell array;
- a voltage generator suitable for generating voltages used for controlling the memory cell array in response to a power-saving signal;
- and
- a control logic suitable for providing the power-saving signal to the voltage generator based on a chip select signal provided from the controller, wherein the control logic includes a delay block suitable for delaying the chip select signal and generating the power-saving signal based on the delayed chip select signal,
- wherein the delay block comprises:
- a first delay block suitable for generating a first delayed signal by delaying the chip select signal by a first delay time;
- a second delay block suitable for determining whether or not the first delayed signal is deactivated for a time longer than a second delay time, and generating a second delayed signal based on the determination result;
- and
- a third delay block suitable for generating the power-saving signal by delaying the second delayed signal by a third delay time,
- wherein the third delay block generates the power-saving signal by delaying the second delayed signal by the third delay time equal to or longer than the second delay time.
11 more elements
Dependencies are inferred from the claim text.