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US 9,318,159 B2Granted
Semiconductor device
AssigneePS4 Lucxo S.a.r.l.
InventorHiroaki Iwaki
Life of this patent
Estimating the term…
Abstract
Disclosed herein is a semiconductor device including a multi-level wiring structure that includes a lower-level wiring, an upper-level wiring and an interlayer insulating film between the lower-level and upper-level wirings. The device further includes a plurality of bit lines for a plurality of memory cells, and each of the bit lines includes a first portion that is formed as the lower-level wiring and a second portion that is electrically connected in series to the first portion and formed as the upper-level wiring.
Claims9
A semiconductor device comprising:
- a first memory mat comprising a plurality of first memory cells;
- a second memory mat comprising a plurality of second memory cells;
- a first global bit line extending over the first memory mat and the second memory mat;
- and
- a second global bit line extending over the first memory mat and the second memory mat;
- a multi-level wiring structure comprising a lower-level wiring, an upper-level wiring, and an interlayer insulation film between the lower-level wiring and the upper-level wiring;
- wherein:
- the first memory mat further comprises:
- a plurality of third memory cells;
- a first local bit line connected to the plurality of first memory cells;
- a third local bit line connected to the plurality of third memory cells;
- a first control signal line which controls a first switching element connecting between
- the first local bit line and the first global bit line;
- and
- a third control signal line which controls a third switching element connecting between
- the third local bit line and the second global bit line;
- the second memory mat further comprises:
- a plurality of fourth memory cells;
- a second local bit line connected to the plurality of second memory cells;
- a fourth local bit line connected to the plurality of fourth memory cells;
- a second control signal line which controls a second switching element connecting
- between the second local bit line and the first global bit line;
- and
- a fourth control signal line which controls a fourth switching element connecting
- between the fourth local bit line and the second global bit line;
- the first global bit line comprises a first portion over the first memory mat and a second portion over the second memory mat, the first portion being formed as the lower-level wiring, and the second portion being formed as the upper-level wiring;
- the second global bit line comprises a third portion over the first memory mat and a fourth portion over the second memory mat, the third portion being formed as the upper-level wiring, the fourth portion being formed as the lower-level wiring;
- the second global bit line is operatively connected to a selected one of the plurality of third memory cells and the plurality of fourth memory cells;
- the first memory mat comprises a first precharge circuit precharging the first local bit line to a predetermined precharge potential and a second precharge circuit precharging the third local bit line to the precharge potential;
- and
- the second memory mat comprises a third precharge circuit precharging the second local bit line to the precharge potential and a fourth precharge circuit precharging the fourth local bit line to the precharge potential.
28 more elements
A semiconductor device comprising:
- a first memory mat that includes:
- first and second sub-mats,
- first and second local bit lines provided for the first and second sub-mats, respectively, and
- first and second sets of memory cells connected to the first and second local bit lines, respectively;
- a multi-level wiring structure including a lower-level wiring, an upper-level wiring and an interlayer insulating film between the lower-level wiring and the upper-level wiring;
- a first global bit line crossing over the first memory mat, the first global bit line including a first portion over the first sub-mat to be operatively connected to the first local bit line and a second portion over the second sub-mat to be operatively connected to the second local bit line, the first portion being formed as the lower-level wiring, and the second portion being formed as the upper-level wiring;
- a second memory mat that includes:
- third and fourth sub-mats,
- third and fourth local bit lines provided for the third and fourth sub-mats, respectively, and
- third and fourth sets of memory cells connected to the third and fourth local bit lines, respectively;
- a second global bit line crossing over the second memory mat, the second global bit line including a third portion over the third sub-mat to be operatively connected to the third local bit line and a fourth portion over the fourth sub-mat to be operatively connected to the fourth local bit line, the third portion being formed as the lower-level wiring, and the fourth portion being formed as the upper-level wiring;
- and
- a first sense amplifier provided between the first and second memory mats and including first and second sense nodes connected to the first and second global bit lines, respectively
- wherein the first memory mat further includes fifth and sixth local bit lines provided for the first and second sub-mats, respectively, and fifth and sixth sets of memory cells connected to the fifth and sixth local bit lines, respectively;
- wherein the second memory mat further includes seventh and eighth local bit lines provided for the third and fourth sub-mats, respectively, and seventh and eighth sets of memory cells connected to the seventh and eighth local bit lines, respectively;
- and
- wherein the device further comprises:
- a third global bit line crossing over the first memory mat in substantially parallel to the first global bit line, the third global bit line including a fifth portion over the first sub-mat to be operatively connected to the fifth local bit line and a sixth portion over the second sub-mat to be operatively connected to the sixth local bit line, the fifth portion being formed as the upper-level wiring, the sixth portion being formed as the lower-level wiring,
- a fourth global bit line crossing over the second memory mat in substantially parallel to the second global bit line, the fourth global bit line including a seventh portion over the third sub-mat to be operatively connected to the seventh local bit line and an eighth portion over the fourth sub-mat to be operatively connected to the eighth local bit line, the seventh portion being formed as the upper-level wiring, the eighth portion being formed as the lower-level wiring, and
- second and third sense amplifiers arranged such that the first and second memory mats are disposed between the second and third sense amplifiers, the third and fourth global bit lines being connected to the second and third sense amplifiers, respectively.
17 more elements
Dependencies are inferred from the claim text.