Non-volatile memory using bi-directional resistive elements

A method of operating a memory cell having a first bi-directional resistive element having a cathode coupled to a first power rail and an anode coupled to an internal node, and a second bi-directional resistive element having a cathode coupled to the internal node and an anode coupled to a second power rail, the method comprising:

• during a read operation:
• coupling the first and second bi-directional resistive elements in series between the first power rail and the second power rail, and
• coupling the internal node to a control electrode of a pull-down transistor configured to draw current from a first bitline based on a difference in resistance between the first and second bi-directional resistive elements;
• and
• during a write operation:
• coupling the internal node to a second bitline, wherein the first bitline and the second bitline are a same bitline,
• setting the first power rail to a first voltage different from a voltage of the second bitline, and
• setting the second power rail to the first voltage.

A memory comprising:

• an array of memory cells, wherein each memory cell comprises:
• a first bi-directional resistive element having a cathode coupled to a first power rail and an anode coupled to an internal node;
• a second bi-directional resistive element having a cathode coupled to the internal node and an anode coupled to a second power rail;
• a first transistor having a control electrode coupled to the internal node, a first current electrode, and a second current electrode coupled to a third power rail;
• a second transistor having a first current electrode coupled to a first bitline, a second current electrode coupled to the first current electrode of the first transistor, and a control electrode coupled to a read wordline;
• and
• a third transistor having a first current electrode coupled to a second bitline, a control electrode coupled to a write wordline, and a second current electrode coupled to the internal node, wherein, in each memory cell of the memory array of memory cells, the first bitline and the second bitline are a same bitline, and one of a group consisting of the second and third power rails are a same power rail, and the first and third power rails are a same power rail;
• column decode circuitry coupled to the first and second power rails, and to the first bitline of each memory cell of the array of memory cells;
• and
• row decode circuitry coupled to the read and write wordlines of each memory cell of the array of memory cells,
• wherein during a write operation, the column decode circuitry is configured to apply a same voltage to the first and second power rails and a different voltage to the first and second bit lines, and for each memory cell coupled to an activated write wordline, the third transistor couples the second bitline to the internal node,
• wherein when the different voltage at the internal node is at least a predetermined amount greater than the same voltage of the first and second power rails, a first resistance state is written simultaneously to the first and second bi-directional elements of the memory cell, and
• when the different voltage at the internal node is at least the predetermined amount less than the same voltage of the first and second power rails, a second resistance state is written simultaneously to the first and second bi-directional elements of the memory cell.