Clock adjusting circuit, memory storage device, and memory control circuit unit

A memory storage device, comprising:

• a connect interface unit, configured to couple to a host system;
• a rewritable non-volatile memory module, comprising a plurality of physical erasing units;
• and
• a memory control circuit unit, coupled to the connect interface unit and the rewritable non-volatile memory module,
• wherein the connect interface unit comprises a clock adjusting circuit, the clock adjusting circuit is disposed on a die, the die has a plurality of layers, and the clock adjusting circuit comprises:
• a detection circuit, configured to detect a signal characteristic difference between an input signal and an output signal to generate a first signal;
• a control voltage generating circuit, coupled to the detection circuit, and configured to generate a control voltage according to the first signal;
• and
• a voltage-controlled oscillator (VCO), coupled to the control voltage generating circuit, and comprising an inductor and a capacitor, wherein the VCO is configured to receive the control voltage and oscillate according to an impedance characteristic of the inductor and the capacitor to generate the output signal,
• wherein the inductor is entirely disposed on a pad layer among the layers.

A memory storage device, comprising:

• a connect interface unit, configured to couple to a host system;
• a rewritable non-volatile memory module, comprising a plurality of physical erasing units;
• and
• a memory control circuit unit, coupled to the connect interface unit and the rewritable non-volatile memory module,
• wherein the connect interface unit comprises an inductor and a capacitor, the inductor is disposed on a first layer of a die, the capacitor is disposed on a second layer of the die, the first layer is different from the second layer, and when viewed from a direction perpendicular to the first layer, the inductor and the capacitor at least partially overlap each other.

A memory control circuit unit comprising:

• a connect interface unit, configured to couple to a host system;
• and
• a memory management circuit coupled to the connect interface unit,
• wherein the connect interface unit comprises a clock adjusting circuit, the clock adjusting circuit is disposed on a die, the die has a plurality of layers, and the clock adjusting circuit comprises:
• a detection circuit, configured to detect a signal characteristic difference between an input signal and an output signal to generate a first signal;
• a control voltage generating circuit, coupled to the detection circuit, and configured to generate a control voltage according to the first signal;
• a voltage-controlled oscillator (VCO), coupled to the control voltage generating circuit, and comprising an inductor and a capacitor, wherein the VCO is configured to receive the control voltage and oscillate according to an impedance characteristic of the inductor and the capacitor to generate the output signal, wherein the inductor is disposed on a pad layer among the layers, and
• a filter, coupled between the control voltage generating circuit and the VCO, wherein the filter comprises a filter capacitor, the filter capacitor is disposed on a first layer among the layers, the first layer is different from the pad layer, and when viewed from a direction perpendicular to the pad layer, the filter capacitor and the inductor at least partially overlap each other.