Display driver precharge circuitry

One or more tangible, non-transitory machine-readable media comprising instructions to:

• cause a first switch of display driver circuitry of an electronic display to become activated during a higher voltage period, thereby outputting a voltage higher than ground to a plurality of display control switches in a display panel of the electronic display or in the display driver circuitry, or both, wherein the plurality of display control switches are coupled in parallel and collectively have a capacitance;
• cause a second switch to become activated during a ground discharge period, the ground discharge period occurring immediately after the higher voltage period, thereby discharging to ground the capacitance of the plurality of display control switches;
• cause a third switch to become activated during a lower voltage period, the lower voltage period occurring immediately after the ground discharge period, thereby outputting a voltage lower than ground to the plurality of display control switches;
• cause a first slew rate control circuitry of the display driver circuitry to control a slew rate of changes in the voltage that is output to the plurality of display control switches by activating different switches of a first plurality of slew rate control switches such that the first slew rate control circuitry provides a different resistance;
• and
• cause a second slew rate control circuitry of the display driver circuitry to control a slew rate of changes in the voltage that is output to the plurality of display control switches by activating different switches of a second plurality of slew rate control switches such that the second slew rate control circuitry provides a different resistance.

A processor configured to generate multiplexed image data;

• and
• an electronic display configured to display the multiplexed image data, wherein the electronic display comprises first timing circuitry configured to control a plurality of demultiplexer switches to demultiplex the image data, wherein gates of the plurality of demultiplexer switches are coupled in parallel, wherein the plurality of demultiplexer switches have a collective capacitance, and wherein the first timing circuitry comprises:
• a first switch coupled to slew rate control circuitry configured to be activated during a higher voltage period and to provide, when activated, a voltage higher than ground to the plurality of demultiplexer switches;
• a second switch coupled to the slew rate control circuitry configured to be activated during a lower voltage period and to provide, when activated, a voltage lower than ground to the plurality of demultiplexer switches;
• and
• a third switch coupled to the slew rate control circuitry configured to become activated during a ground discharge period and a ground precharge period and to provide, when activated, a ground voltage to the plurality of demultiplexer switches;
• wherein the higher voltage period is configured to occur immediately after the ground precharge period, the ground discharge period is configured to occur immediately after the higher voltage period, the lower voltage period is configured to occur immediately after the ground discharge period, and the ground precharge period is configured to occur immediately after the lower voltage period, and
• wherein the periods are configured to repeat;
• wherein the slew rate control circuitry comprises shared slew rate control circuitry comprising:
• a plurality of pass-gate slew rate control switches coupled to one another;
• and
• a plurality of resistances coupled in series to one another;
• wherein an input of all of the plurality of pass-gate slew rate control switches is coupled to a common output of the first, second, and third switches and wherein an output of each of the plurality of pass-gate slew rate control switches is respectively coupled before or after one of the plurality of resistances, such that activating different switches of the plurality of pass-gate slew rate control switches causes the shared slew rate control circuitry to provide a different resistance.

A timing circuit for providing a timing signal to control a plurality of gates of display control circuitry of an electronic display, the plurality of gates of the display control circuitry having a collective capacitance, the timing circuit comprising:

• a first switch coupled between a positive voltage supply node and slew rate control circuitry;
• a second switch coupled between a negative voltage supply node and the slew rate control circuitry;
• and
• a third switch coupled between a ground node and the slew rate control circuitry;
• wherein the slew rate control circuitry is configured to output the timing control signal to the plurality of gates of the display control circuitry and control a slew rate of the timing signal;
• wherein the slew rate control circuitry comprises:
• first slew rate control circuitry coupled between the first switch and the plurality of gates of the display control circuitry, wherein the first slew rate control circuitry is configured to control a rise time of the timing signal output to the plurality of gates of the display when the first switch is activated following deactivation of the third switch;
• and
• second slew rate control circuitry coupled between the second switch and the plurality of gates of the display control circuitry and between the third switch and the plurality of gates of the display control circuitry, wherein the first slew rate control circuitry is configured to control:
• a fall time of the timing signal output to the plurality of gates of the display when the second switch is activated following the deactivation of the third switch;
• a fall time of the timing signal output to the plurality of gates of the display when the third switch is activated following deactivation of the first switch;
• and
• a rise time of the timing signal output to the plurality of gates of the display when the third switch is activated following deactivation of the second switch.