SM3 hash algorithm acceleration processors, methods, systems, and instructions

A system to process instructions comprising:

• an interconnect;
• a processor coupled with the interconnect, the processor to receive a two round state word update instruction for an SM3 hash algorithm, wherein the SM3 hash algorithm utilizes a parameter Tj having a hexadecimal value of 79cc4519 for a first set of rounds and a hexadecimal value of 79cc4519 for a second set of rounds, the two round state word update instruction to indicate one or more source packed data operands, the one or more source packed data operands to have eight 32-bit state words Aj, Bj, Cj, Dj, Ej, Fj, Gj, and Hj that are to correspond to a round (j) of the SM3 hash algorithm, and the one or more source packed data operands to have a set of messages that are sufficient to evaluate two rounds of the SM3 hash algorithm, the processor, in response to the two round state word update instruction, to store one or more result packed data operands, in one or more destination storage locations that are to be indicated by the two round state word update instruction,
• the one or more result packed data operands to have at least four state words Aj+2, Bj+2, Ej+2, and Fj+2, which respectively have been updated by two rounds of the SM3 hash algorithm relative to the four 32-bit state words Aj, Bj, Ej, and Fj;
• and
• a dynamic random access memory (DRAM) coupled with the interconnect, the DRAM storing a set of instructions to implement the SM3 hash algorithm, the set of instructions, when executed by the processor, to cause the processor to perform operations comprising:
• using Aj, Bj, Ej and Fj to generate Cj+2, Dj+2, Gj+2, and Hj+2, which respectively have been updated by two rounds of the SM3 hash algorithm relative to Cj, Dj, Gj, and Hj.

An article of manufacture comprising a non-transitory machine-readable storage medium, the non-transitory machine-readable storage medium storing an SM3 two round state word update instruction,

• the SM3 two round state word update instruction to indicate one or more source packed data operands, the one or more source packed data operands to have eight 32-bit state words Aj, Bj, Cj, Dj, Ej, Fj, Gj, and Hj for a round (j) of an SM3 hash algorithm, and the one or more source packed data operands to have four messages sufficient to evaluate two rounds of the SM3 hash algorithm, and the SM3 two round state word update instruction if executed by a machine is to cause the machine to perform operations comprising:
• generating at least four two-round updated 32-bit state words Aj+2, Bj+2, Ej+2, and Fj+2, which respectively have been updated by two rounds of the SM3 hash algorithm relative to Aj, Bj, Ej, and Fj;
• and
• storing the at least four 32-bit state words Aj+2, Bj+2, Ej+2, and Fj+2 in one or more destination storage locations that are to be indicated by the SM3 two round state word update instruction.