US 9,317,650 B2 · Double patterning technology (DPT) layout routing

Abstract

One or more techniques or systems for determining double patterning technology (DPT) layout routing compliance are provided herein. For example, a layout routing component of a system is configured to assign a pin loop value to a pin loop. In some embodiments, the pin loop value is assigned based on a mask assignment of a pin of the pin loop. In some embodiments, the pin loop value is assigned based on a number of nodes associated with the pin loop. DPT compliance or a DPT violation is determined for the pin loop based on the pin loop value. In this manner, odd loop detection associated with DPT layout routing is provided because a DPT violation results in generation of an additional instance of a net, for example. Detecting an odd loop allows a design to be redesigned before fabrication, where the odd loop would present undesired issues.

Claims20

Dependent claims

A system for determining double patterning technology (DPT) layout routing compliance, comprising:

a layout routing component configured to:
create a first pin group comprising a first set of one or more pre-colored pins that are linked together by a first set of internal conflict spaces;
associate the first pin group with a first phantom assisted feature (AF) mask polygon, the associating comprising:
selecting a first pre-colored pin from the first set of one or more pre-colored pins;
determining a first mask assignment associated with the first pre-colored pin;
and
assigning the first phantom AF mask polygon to a different mask than a mask for the first pre-colored pin according to the first mask assignment;
create a pin loop based on the first pre-colored pin and the phantom AF mask polygon;
assign a pin loop value to the pin loop;
and
determine whether a double patterning technology (DPT) violation is present for the pin loop based on the pin loop value.

8 more elements

A computer-readable storage medium comprising computer-executable instructions, which when executed at least in part via a processing unit performs acts, comprising:

creating a first pin group based on at least one of a mask assignment for one or more pins of the first pin group or one or more first internal conflict spaces between at least some of the one or more pins of the first pin group;
creating a second pin group based on at least one of a mask assignment for one or more pins of the second pin group or one or more second internal conflict spaces between at least some of the one or more pins of the second pin group;
associating at least one of the first pin group or the second pin group with at least one of a first phantom assisted feature (AF) mask or a second phantom AF mask;
generating at least one of a first net for a pin of the first pin group or a second net for a pin of the second pin group;
creating a pin loop based on at least one of the first net, the second net, the first phantom AF mask, the second phantom AF mask, at least some of the one or more first internal conflict spaces, or at least some of the one or more second internal conflict spaces;
assigning a pin loop value to the pin loop based on a number of nodes associated with the pin loop;
and
determining at least one of a double patterning technology (DPT) compliance for the pin loop or a DPT violation for the pin loop based on the pin loop value.

5 more elements

Dependencies are inferred from the claim text.

Double patterning technology (DPT) layout routing

Life of this patent

Double patterning technology (DPT) layout routing

Life of this patent

Abstract

Claims20