Masks formed based on integrated circuit layout design having cell that includes extended active region
AssigneeTaiwan Semiconductor Manufacturing Company, Ltd.
InventorsLee-Chung Lu, Li-Chun Tien, Hui-Zhong Zhuang, Chang-Yu Wu
Life of this patent
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Abstract
A set of masks corresponds to an integrated circuit layout. The integrated circuit layout includes a first cell having a first transistor region and a second transistor region, and a second cell having a third transistor region and a fourth transistor region. The first cell and the second cell adjoin each other at side cell boundaries thereof, the first transistor region and the third transistor region are formed in a first continuous active region, and the second transistor region and the fourth transistor region are formed in a second continuous active region. The set of masks is formed based on the integrated circuit layout.
Claims20
A set of masks corresponding to an integrated circuit layout, the integrated circuit layout comprising:
- a first cell comprising a first transistor region and a second transistor region;
- a second cell comprising a third transistor region and a fourth transistor region,
- wherein
- the first cell and the second cell adjoin each other at side cell boundaries thereof,
- the first transistor region and the third transistor region are formed in a first continuous active region, and
- the second transistor region and the fourth transistor region are formed in a second continuous active region;
- and
- a middle gate strip extending from the first transistor region to the second transistor region, along a line at which the first cell adjoins the second cell,
- wherein the set of masks is formed based on the integrated circuit layout.
A set of masks corresponding to an integrated circuit layout, the integrated circuit layout comprising:
- a first cell comprising a first active region and a first side boundary;
- a second cell comprising a second active region and a second side boundary along the first side boundary;
- a first gate strip in the first cell parallel to the first side boundary and overlying the first active region;
- a second gate strip in the second cell parallel to the second side boundary and overlying the second active region;
- and
- a dummy gate strip parallel to and between the first gate strip and the second gate strip,
- wherein the dummy gate strip overlies one of the first active region or the second active region,
- wherein the set of masks is formed based on the integrated circuit layout.
A set of masks corresponding to an integrated circuit layout, the integrated circuit layout comprising:
- a first cell comprising a first active region and a first side boundary;
- a second cell comprising a second active region and a second side boundary along the first side boundary;
- a first gate strip in the first cell parallel to the first side boundary and overlying the first active region;
- a second gate strip in the second cell parallel to the second side boundary and overlying the second active region;
- a blank region abutting the first active region and the second active region;
- a first dummy gate strip in the first cell between the first gate strip and the first side boundary, and overlying the first active region and the blank region;
- and
- a second dummy gate strip in the second cell between the second gate strip and the second side boundary, and overlying the second active region and the blank region,
- wherein the set of masks is formed based on the integrated circuit layout.
Dependencies are inferred from the claim text.