US 9,317,644 B2 · Generating capacitance look-up tables for wiring patterns in the presence of metal fills

Abstract

A computer system selects a signal conductor from an electronic circuit design layout and assigns a first potential to the selected signal conductor. Next, the computer system assigns a second potential to other signal conductors included in the electronic circuit design layout. The computer system then selects a metal fill from the electronic circuit design layout, which is void from carrying an electrical signal, and generates a zero charge equation for the selected metal fill. The zero charge equation establishes that a total charge residing on the selected metal fill is equal to zero. The computer system includes the zero charge equation in a system of equations, which includes grid point potential equations, and solves the system of equations. In turn, the computer system computes capacitance values for the signal conductors based upon the system of equation solutions, and simulates the electronic circuit design layout using the computed capacitance values.

Claims20

Dependent claims

A computer-implemented method to simulate an electronic design layout comprising:

retrieving an electronic design layout that identifies a plurality of signal conductors and a plurality of metal fills;
positioning, by one or more processing devices, metal fill grid points on one or more of the plurality of metal fills;
selecting one of the plurality of metal fills to establish a selected metal fill;
assigning a metal fill surface potential variable to at least one of the metal fill grid points;
generating, by the one or more of the processing devices, a zero charge equation for the selected metal fill, wherein the equation relates the metal fill surface potential variable to neighboring metal fill grid points around a metal fill boundary of the selected metal fill;
generating, by the one or more of the processing devices, one or more capacitance values corresponding to one or more of the plurality of signal conductors using the zero charge equation;
and
simulating, by the one or more of the processing devices, the electronic design layout using the generated one or more capacitance values.

5 more elements

An information handling system that simulates an electronic design layout, the information handling system comprising:

one or more processors;
a memory accessible by at least one of the one or more processors;
a nonvolatile storage area accessible by at least one of the one or more processors;
wherein the memory stores a set of instructions which, when executed by the one or more processors, perform actions of:
retrieving an electronic design layout from the nonvolatile storage area that identifies a plurality of signal conductors and a plurality of metal fills;
selecting one of the plurality of metal fills to establish a selected metal fill;
generating a zero charge equation for the selected metal fill, wherein the equation relates a metal fill surface potential variable of the selected metal fill to neighboring metal fill grid points around a metal fill boundary of the selected metal fill;
generating one or more capacitance values corresponding to one or more of the plurality of signal conductors using the zero charge equation;
and
simulating the electronic design layout using the generated one or more capacitance values.

7 more elements

A computer readable storage medium having a computer program product stored thereon, the computer program product comprising instructions which, when executed by an information handling system, causes the information handling system to perform actions that include:

retrieving an electronic design layout that identifies a plurality of signal conductors and a plurality of metal fills;
positioning, by one or more processing devices, metal fill grid points on one or more of the plurality of metal fills;
selecting one of the plurality of metal fills to establish a selected metal fill;
assigning a metal fill surface potential variable to at least one of the metal fill grid points;
generating, by the one or more processing devices, a zero charge equation for the selected metal fill, wherein the equation relates the metal fill surface potential variable to neighboring metal fill grid points around a metal fill boundary of the select metal fill;
generating, by the one or more processing devices, one or more capacitance values corresponding to one or more of the plurality of signal conductors using the zero charge equation;
and
simulating, by the one or more processing devices, the electronic design layout using the generated one or more capacitance values.

5 more elements

Dependencies are inferred from the claim text.

Generating capacitance look-up tables for wiring patterns in the presence of metal fills

Life of this patent

Generating capacitance look-up tables for wiring patterns in the presence of metal fills

Life of this patent

Abstract

Claims20