Gate substitution based system and method for integrated circuit power and timing optimization

A method of selecting gates for an integrated circuit design comprising:

• identifying, by at least one processing device, gates of the integrated circuit design having a slack value less than a predefined slack threshold;
• and
• for each of the identified gates,
• determining, by at least one processing device, a benefit count or benefit amount based on slack improvements associated with swapping the gate with an alternative implementation having a reduced delay, and
• swapping, by at least one processing device, the gate with the alternative implementation having the reduced delay if the benefit count or benefit amount is greater than a corresponding predetermined benefit threshold.

A computer readable medium comprising instructions stored thereon for directing one or more computers to

• identify gates of an integrated circuit design having a slack value less than a predefined slack threshold;
• and
• for each of the identified gates,
• determine a benefit count or benefit amount based on slack improvements associated with swapping the gate with an alternative implementation having a reduced delay, and
• swap the gate with the alternative implementation having the reduced delay if the benefit count or benefit amount is greater than a corresponding predetermined benefit threshold.