US 9,317,475 B2 · Multiplexing auxiliary processing element and semiconductor integrated circuit

Abstract

A multiplexing auxiliary processing element (PE) performs a process that includes the operations of receiving signals of a plurality of upstream processing elements (PEs) including a plurality of pairs of PEs arranged on the input side; supplying the signals from the upstream PEs to a multiplex PE that is multiplexed and used so that the signals are subjected to a predetermined process by the multiplex PE; receiving the processed signals subjected to the predetermined process by the multiplex PE and sequentially supplying the signals to a plurality of downstream PEs arranged on the output side; and performing operations of the upstream PEs synchronously with the supply of the processed signals to the corresponding downstream PEs on the basis of setting of the multiplexing auxiliary PE.

Claims13

Dependent claims

A method of using a multiplexing auxiliary processing element (PE), comprising:

receiving input signals from a plurality of upstream processing elements (PEs) arranged on an input side, wherein each of the input signals includes a plurality of data bits and one or more valid signal bits;
comparing the one or more valid signal bits with a configuration signal;
if a predetermined condition is satisfied, supplying the input signals to a multiplex PE, wherein the multiplex PE processes the input signals to generate processed signals;
delaying the one or more valid signal bits by a designated cycle;
receiving, from the multiplex PE, the processed signals;
and
supplying, in accordance with the delayed one or more valid signal bits, the processed signals to a plurality of downstream PEs arranged on an output side.

4 more elements

A semiconductor integrated circuit, comprising:

a plurality of upstream processing elements (PEs);
a plurality of downstream PEs;
a multiplex processing element (PE);
and
a multiplexing auxiliary PE configured to:
receive input signals from the upstream PEs arranged on an input side, wherein each of the input signals includes a plurality of data bits and one or more valid signal bits;
compare the one or more valid signal bits with a configuration signal;
if a predetermined condition is satisfied, supply the input signals to the multiplex PE, wherein the multiplex PE processes the input signals to generate processed signals;
delay the one or more valid signal bits by a designated cycle;
receive, from the multiplex PE, the processed signals;
and
supply, in accordance with the one or more valid signal bits, the processed signals to the downstream PEs arranged on an output side.

9 more elements

Dependencies are inferred from the claim text.

Multiplexing auxiliary processing element and semiconductor integrated circuit

Life of this patent

Multiplexing auxiliary processing element and semiconductor integrated circuit

Life of this patent

Abstract

Claims13