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US 9,317,464 B2Granted
Method, apparatus and system for configuring coupling with input-output contacts of an integrated circuit
AssigneeIntel Corporation
InventorsChristopher E. Cox, Kuljit S. Bains
Life of this patent
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Abstract
Techniques and mechanisms for configuring an integrated circuit to couple to, and exchange data with, a hardware interface. In an embodiment, the integrated circuit comprises a data channel including a plurality of bits, configuration logic, and a plurality of contacts including a first contact group and a second contact group. In response to a signal indicating connectivity of the integrated circuit to the interface, a mode of the configuration logic is selected to couple the plurality of bits to one of the first contact group and the second contact group.
Claims24
An integrated circuit chip comprising:
- a memory array;
- a data channel including a first plurality of bit lines comprising a first bit line and a second bit line;
- configuration logic coupled to the memory array via the data channel;
- a plurality of input/output (I/O) contacts coupled to the data channel via the configuration logic, the plurality of I/O contacts including a first I/O contact and a second I/O contact;
- and
- detector logic to detect a signal indicating connectivity of an interface to the integrated circuit chip via the plurality of I/O contacts and, in response to the signal, to select one of a plurality of modes of the configuration logic, the plurality of modes including:
- a first mode wherein the first plurality of bit lines are coupled to participate in data exchanges with a first group of I/O contacts of the plurality of I/O contacts, wherein the first bit line is coupled to exchange data with the first I/O contact;
- and
- a second mode wherein the first plurality of bit lines are coupled to participate in data exchanges with a second group of I/O contacts of the plurality of I/O contacts, wherein the first bit line is coupled to exchange data with the second I/O contact.
6 more elements
A method at an integrated circuit chip, the method comprising:
- detecting a signal indicating connectivity of an interface to the integrated circuit chip via a plurality of input/output (I/O) contacts of the integrated circuit, the plurality of I/O contacts including a first I/O contact and a second I/O contact;
- in response to the signal, selecting one of a plurality of modes of configuration logic of the integrated circuit, the configuration logic coupled to a memory array of the integrated circuit chip via a data channel including a first plurality of bit lines comprising a first bit line and a second bit line, the plurality of modes including:
- a first mode wherein the first plurality of bit lines are coupled to participate in data exchanges with a first group of I/O contacts of the plurality of I/O contacts, wherein the first bit line is coupled to the first I/O contact;
- and
- a second mode wherein the first plurality of bit lines are coupled to participate in data exchanges with a second group of I/O contacts of the plurality of I/O contacts, wherein the first bit line is coupled to the second I/O contact;
- and
- configuring the selected one of the plurality of modes of the configuration logic.
4 more elements
A packaged memory device comprising:
- a hardware interface;
- and
- a first integrated circuit chip coupled to the hardware interface, the first integrated circuit chip including:
- a memory array;
- a data channel including a first plurality of bit lines comprising a first bit line and a second bit line;
- configuration logic coupled to the memory array via the data channel;
- a plurality of input/output (I/O) contacts coupled to the data channel via the configuration logic;
- and
- detector logic to detect a signal indicating connectivity of the hardware interface to the first integrated circuit chip via the plurality of I/O contacts and, in response to the signal, to select one of a plurality of modes of the configuration logic, the plurality of modes including:
- a first mode wherein the first plurality of bit lines are coupled to participate in data exchanges with a first group of I/O contacts of the plurality of I/O contacts, wherein the first bit line is coupled to the first I/O contact;
- and
- a second mode wherein the first plurality of bit lines are coupled to participate in data exchanges with a second group of I/O contacts of the plurality of I/O contacts, wherein the first bit line is coupled to the second I/O contact.
9 more elements
Dependencies are inferred from the claim text.