Multi-level paging and address translation in a network environment
AssigneeCisco Technology, Inc.
InventorSagar Borikar
Life of this patent
Estimating the term…
Abstract
An example method for facilitating multi-level paging and address translation in a network environment is provided and includes receiving a request for memory in a physical memory of a network element, associating the request with a first virtual address space, mapping a memory region located in the physical memory to a first window in the first virtual address space, the memory region being also mapped to a second window in a different, second virtual address space, remapping the first window in the first virtual address space to the second window in the second virtual address space, and responding to the request with addresses of the second window in the second virtual address space.
Claims20
A method executed at a network element having a processor, comprising:
- receiving a request for memory in a physical memory of the network element;
- associating the request with a first virtual address space;
- mapping a memory region located in the physical memory to a first window in the first virtual address space, the memory region being also mapped to a second window in a different, second virtual address space;
- remapping the first window in the first virtual address space to the second window in the second virtual address space;
- and
- responding to the request with addresses of the second window in the second virtual address space.
Non-transitory tangible media that includes instructions for execution, which when executed by a processor of a network element, is operable to perform operations comprising:
- receiving a request for memory in a physical memory of the network element;
- associating the request with a first virtual address space;
- mapping a memory region located in the physical memory to a first window in the first virtual address space, the memory region being also mapped to a second window in a different, second virtual address space;
- remapping the first window in the first virtual address space to the second window in the second virtual address space;
- and
- responding to the request with addresses of the second window in the second virtual address space.
An apparatus, comprising:
- a physical memory for storing data;
- and
- a processor, wherein the processor executes instructions associated with the data, wherein the processor and the physical memory cooperate, such that the apparatus is configured for:
- receiving a request for memory in the physical memory;
- associating the request with a first virtual address space;
- mapping a memory region located in the physical memory to a first window in the first virtual address space, the memory region being also mapped to a second window in a different, second virtual address space;
- remapping the first window in the first virtual address space to the second window in the second virtual address space;
- and
- responding to the request with addresses of the second window in the second virtual address space.
Dependencies are inferred from the claim text.