Latency reduction for direct memory access operations involving address translation
AssigneeVMware, Inc.
InventorsBhavesh Davda, Benjamin Charles Serebrin
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AssigneeVMware, Inc.
InventorsBhavesh Davda, Benjamin Charles Serebrin
Estimating the term…
Latency reduction for direct memory access operations involving address translation is disclosed. Example methods disclosed herein to perform direct memory access (DMA) operations include initializing a ring of descriptors, the descriptors to index respective buffers for storing, in a first memory, data to be transmitted. Such example methods also include causing prefetching of a first address translation associated with a second descriptor in the ring of descriptors to be performed after a first DMA operation is performed to retrieve, for transmission, first data from a first buffer indexed by a first descriptor in the ring of descriptors and before second data is determined to be ready for transmission, the first address translation being associated with a second DMA operation for retrieving the second data from the first memory.
A method to perform direct memory access (DMA) operations, the method comprising:
A tangible machine readable storage medium comprising machine readable instructions which, when executed, cause a machine to at least:
An apparatus to perform direct memory access (DMA) operations, the apparatus comprising:
A method comprising:
A tangible machine readable storage medium comprising machine readable instructions which, when executed, cause a machine to at least:
An apparatus comprising:
Dependencies are inferred from the claim text.