System supporting multiple partitions with differing translation formats

#One or more aspects relate, in general, to memory of a computing environment, and in particular, to facilitating access to the memory.

#System configurations include physical memory used to store applications and data. The amount of physical memory is fixed and often inadequate to support the needs of users. Therefore, to provide additional memory or at least the appearance of additional memory, a memory management technique, referred to as virtual memory, is utilized. Virtual memory uses virtual addressing, which provides ranges of addresses that can appear to be much larger than the physical size of main memory.

#To access main memory in a system configuration that includes virtual memory, a memory access is requested that includes an effective address. The effective address is translated into a real address used to access the physical memory.

#One or more aspects are particularly pointed out and distinctly claimed as examples in the claims at the conclusion of the specification. The foregoing and objects, features, and advantages of one or more aspects are apparent from the following detailed description taken in conjunction with the accompanying drawings in which:

#FIG. 1A depicts one example of a computing environment;

#FIG. 1B depicts another example of a computing environment;

#In one aspect, a system configuration is provided that has different types of translation structures available to it for use in translating memory addresses from one format (e.g., an effective address, and in particular, a virtual address associated therewith) to another format (e.g., a real address). Multiple translation structure formats (e.g., multiple page table formats, such as hash page tables and hierarchical page tables) are concurrently supported in a system configuration. In one embodiment, the different types of translation structures are structurally different, and include, for instance, hash structures, hierarchical structures and/or offset structures, which are described herein.

#Further, in one aspect, a system configuration is provided that includes multiple partitions that have differing translation mechanisms associated therewith. For instance, one partition has associated therewith a single level translation mechanism for translating guest virtual addresses to host physical addresses, and another partition has a nested level translation mechanism for translating guest virtual addresses to host physical addresses. The different translation mechanisms and partitions are supported by a single hypervisor. The hypervisor is, for instance, a paravirtualized hypervisor. Thus, in one aspect, faults, including host translation faults, associated with address translation of guest memory addresses in a single level translation mechanism are managed, at least in part, by the guest operating system. However, full virtualization is also provided for those partitions using nested level translations of guest memory addresses. The host translation faults are handled entirely by the host without (or independent of) assistance from the guest operating system. With full virtualization, the guest operating system is not involved in managing address translation faults resulting from host level translations. To support full virtualization by a paravirtualization hypervisor, an adjunct component is provided that facilitates handling of address translation faults resulting from host level translations. As used herein, an adjunct component is a helper component connected, added or coupled to an entity, typically in an auxiliary manner, and not limited to any specific adjunct architecture.

#Computing environments of different architectures may incorporate and use one or more aspects provided herein. For instance, environments based on the PowerPC architecture, also referred to as Power ISA, offered by International Business Machines Corporation and described in the Power ISA™ Version 2.06 Revision B specification, Jul. 23, 2010, incorporated herein by reference in its entirety, may include one or more aspects, as well as computing environments of other architectures, such as the z/Architecture, offered by International Business Machines Corporation, and described in z/Architecture—Principles of Operation, Publication No. SA22-7932-08, 9th Edition, August 2010, which is hereby incorporated herein by reference in its entirety.