Cache memory apparatus, cache control method, and microprocessor system
AssigneeRenesas Electronics Corporation
InventorTakashi Kitahara
Life of this patent
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Abstract
A cache memory apparatus according to the present invention includes a cache memory that caches an instruction code corresponding to a fetch address and a cache control circuit that controls the instruction code to be cached in the cache memory. The cache control circuit caches an instruction code corresponding to a subroutine when the fetch address indicates a branch into the subroutine and disables the instruction code to be cached when the number of the instruction codes to be cached exceeds a previously set maximum number.
Claims13
A cache memory apparatus comprising;
- a cache memory that caches an instruction code corresponding to a fetch address;
- and
- a cache control circuit that controls the instruction code to be cached in the cache memory, wherein the cache control circuit:
- caches the instruction code corresponding to a subroutine when the fetch address indicates a branch into the subroutine, and
- disables the instruction code to be cached when a number of instruction codes to be cached exceeds a previously set maximum number;
- and
- wherein the previously set maximum number of the instruction codes is obtained by dividing a number of clocks since a CPU outputs the fetch address to a memory until the memory outputs the instruction code by a number of clocks necessary for the CPU to execute one instruction code.
A microprocessor system comprising:
- a CPU;
- a memory that stores an instruction code to be executed in the CPU;
- a cache memory that caches the instruction code corresponding to a fetch address output from the CPU;
- and
- a cache control circuit that controls the instruction code to be cached in the cache memory, wherein the cache control circuit:
- caches the instruction code corresponding to the subroutine when the fetch address indicates a branch into a subroutine, and
- disables the instruction code to be cached when a number of the instruction codes to be cached exceeds a previously set maximum number;
- and
- wherein the previously set maximum number of the instruction codes is obtained by dividing a number of clocks since a CPU outputs the fetch address to a memory until the memory outputs the instruction code by a number of clocks necessary for the CPU to execute one instruction code.
A cache control method for a cache memory that caches an instruction code corresponding to a fetch address, the cache control method comprising:
- caching the instruction code corresponding to a subroutine when the fetch address indicates a branch into the subroutine;
- and
- disabling the instruction code to be cached when a number of the instruction codes to be cached exceeds a previously set maximum number, and
- wherein the previously set maximum number of the instruction codes is obtained by dividing a number of clocks since a CPU outputs the fetch address to a memory until the memory outputs the instruction code by a number of clocks necessary for the CPU to execute one instruction code.
Dependencies are inferred from the claim text.