Apparatus and method for controlling the reliability stress rate on a processor
AssigneeIntel Corporation
InventorsDorit Shapira, Krishnakanth V. Sistla, Efraim Rotem, Nadav Shulman, Shmulik Zobel, Allen Chu
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Abstract
An apparatus and method for tracking stress on a processor and responsively controlling operating conditions. For example, one embodiment of a processor comprises: stress tracking logic to determine stress experienced by one or more portions of the processor based on current operating conditions of the one or more portions of the processor; and stress control logic to control one or more operating characteristics of the processor based on the determined stress and a target stress accumulation rate.
Claims21
A processor comprising:
- stress tracking logic to determine stress experienced by one or more portions of the processor based on current operating conditions of the one or more portions of the processor;
- and
- stress control logic to control one or more operating characteristics of the processor based on the determined stress and a target stress accumulation rate;
- wherein the stress tracking logic includes a first meter to determine a first stress related to a first voltage and a second meter to determine an accumulated time-dependent dielectric breakdown (TDDB) stress related to a second voltage.
A method comprising:
- determining stress experienced by one or more portions of a processor based on current operating conditions of the one or more portions of the processor;
- and
- controlling one or more operating characteristics of the processor based on the determined stress and a target stress accumulation rate;
- wherein determining stress comprises determining a first stress related to a first voltage and determining an accumulated time-dependent dielectric breakdown (TDDB) stress related to a second voltage.
A system comprising:
- a memory to store instructions and data;
- a cache having a plurality of cache levels to cache the instructions and data;
- and
- a processor comprising:
- stress tracking logic to determine stress experienced by one or more portions of the processor based on current operating conditions of the one or more portions of the processor, the current operating conditions based, at least in part, on the execution of the instructions and processing of the data;
- and
- stress control logic to control one or more operating characteristics of the processor based on the determined stress and a target stress accumulation rate;
- wherein the stress tracking logic includes a first meter to determine a first stress related to a first voltage and a second meter to determine an accumulated time-dependent dielectric breakdown (TDDB) stress related to a second voltage.
Dependencies are inferred from the claim text.