Protocol checking logic circuit for memory system reliability

#This invention relates generally to memory systems, and more particularly to memory systems which include a memory buffer that serves as an interface between a host controller and memory devices or other memory buffering devices residing on a DIMM, the memory buffer being optionally located on the DIMM itself or as part of the motherboard on which the DIMM connectors are also located.

#Traditional computer systems, such as servers, workstations, desktops and laptops, all use pluggable memory which can be inserted into slots on the computer's motherboard as needed. The most common form of pluggable memory is the Dual In-line Memory Module (DIMM). Historically, DIMMs contain multiple RAM chips—typically DRAM—each of which has a data bus width of 4 or 8 bits. Typically, eight or nine 8-bit DRAM chips (or twice as many 4-bit DRAM chips) are arranged in parallel to provide each DIMM with a total data bus width of 64 or 72 bits; the data bus, typically referred to as the ‘DQ’ bus, is connected to a host controller. Each arrangement of 64 or 72 data bits using DRAM chips in parallel is termed a ‘rank’.

#A command/address (CA) bus also runs between the host controller and each DIMM; the CA and DQ busses together form a ‘system’ bus. With a basic unbuffered DIMM, the CA bus is connected to every DRAM on the DIMM. As a result, there is a high electrical load on the CA bus, given by the product of the number of DRAMs times the number of ranks. For the DQ bus, the number of electrical loads is equal to the number of ranks.

#FIG. 1 illustrates a baseline memory system that comprises of a host memory controller according to an embodiment of the present invention.

#FIG. 2 illustrates a Fully Buffered DIMM Memory system that utilizes the Advanced Memory Buffer (AMB), connected to DDR2 SDRAM devices according to an embodiment of the present invention.

#FIGS. 3A and 3B show a state diagram of a DDR3 SDRAM device. The state diagram is an illustrative example of the behavior of a given memory device as it responds to specific commands in transitioning from state to state.

#The present invention relates to memory storage systems and devices.

#FIG. 1 illustrates a baseline memory system that consists of a host memory controller, 100, a memory interface circuit 110, and multiple memory devices 120. One example of the memory interface circuit 110 illustrated is a DDR3 Registering Clock Driver (RCD). A second example of the memory interface circuit 110 illustrated is a DDR4 Registering Clock Driver (RCD). The description of the memory interface circuit 110 is generic in nature, and many other circuits may be broadly categorized as a memory interface circuit. Moreover, the use of the DDR3 Registering Clock Driver should be considered as illustrative, and the invention may be broadly applicable to other types of memory devices. In the baseline memory system, the host controller 100 issues commands to the memory interface circuit 110, and the memory interface circuit checks the parity and in turn re-drives the command and address signals to the memory devices 120. In the case that the parity is incorrect, the output driver block 112 may block the erroneous command to the DRAM devices.

#The issue with the baseline memory system is that the command and address bus is protected only with simple parity scheme. In general, simple parity schemes, such as the one illustrated in FIG. 1, protect against the case of the incorrect delivery of a single signal. However, in the case of a catastrophic failure of the host memory controller 100, the command, address and parity inputs may fluctuate randomly, resembling randomized command and address transmissions. In such cases, at the instance of host memory controller failure, unintended commands may be re-driven to the memory devices, illustrated as 120.