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US 9,317,365 B2Granted
Soft decoding of polar codes
AssigneeSeagate Technology LLC
InventorsAbdelHakim S. Alhussien, Erich F. Haratsch, Yue Li
Life of this patent
Estimating the term…
Abstract
An apparatus having a circuit and an interface to a nonvolatile memory is disclosed. The circuit is configured to (i) read a plurality of bits in a read channel of the nonvolatile memory. The bits are encoded with a polar code. The circuit is also configured to (ii) generate a plurality of probabilities based on a plurality of log likelihood ratio values of the read channel and (iii) decode the bits based on the probabilities.
Claims20
An apparatus comprising:
- an interface configured to process a plurality of read/write operations to/from a memory;
- and
- a control circuit configured to (i) read a plurality of bits in a read channel of the memory, wherein the plurality of bits are encoded with a polar code, (ii) generate a plurality of probabilities of transition errors between two possible states of the plurality of bits based on a plurality of log likelihood ratio values of the read channel of the memory and (iii) decode the plurality of bits based on the plurality of probabilities of transition errors.
A method for soft decoding of a polar code, comprising the steps of:
- reading a plurality of bits in a read channel of a memory, wherein the plurality of bits are encoded with the polar code;
- generating a plurality of probabilities of transition errors between two possible states of the plurality of bits based on a plurality of log likelihood ratio values of the read channel of the memory;
- and
- decoding the plurality of bits based on the plurality of probabilities of transition errors.
1 more element
An apparatus comprising:
- a memory configured to store data;
- and
- a controller configured to (i) process a plurality of input/output requests to read/write to/from the memory, (ii) read a plurality of bits in a read channel of the memory, wherein the plurality of bits are encoded with a polar code, (iii) generate a plurality of probabilities of transition errors between two possible states of the plurality of bits based on a plurality of log likelihood ratio values of the read channel of the memory and (iv) decode the plurality of bits based on the plurality of probabilities of transition errors.
Dependencies are inferred from the claim text.