Memory controller with distribution transformer

A method comprising:

• receiving data of a first length to be stored in a memory, wherein the data has a distribution of m1:n1 ratio for bits having a first logic value and bits having a second logic value, where m1 and n1 are real numbers, wherein the memory comprises a plurality of memory cells that require a first amount of power to set a memory cell to the first logic value, and a second amount of power to set the memory cell to the second logic value, wherein the second amount of power is greater than the first amount of power;
• transforming the data into skewed data, wherein the skewed data has a second length and a distribution of m2:n2 ratio for bits having the first logic value and bits having the second logic value, where the second length is longer than the first length, m2 and n2 are real numbers that are different from one another, with m2 greater than m1 and n2 is smaller than n1, wherein m2 and n2 are selected in view of the first and second amount of power required to set a memory cell to the first or second logic value;
• and
• writing the skewed data into the memory, using less power than writing the data into the memory.

A system comprising:

• a memory;
• a write circuit coupled to the memory, the write circuit including a distribution transformer circuit to:
• receive data of first length to be stored into the memory, wherein the memory comprises a plurality of memory cells that require a first amount of power to set a memory cell to a logic 0, and a second amount of power to set the memory cell to a logic 1, wherein the second amount of power is greater than the first amount of power;
• and
• transform the data into skewed data, wherein the skewed data has a second length, and a distribution of m2:n2 ratio for logic 0 bits and logic 1 bits, where the second length is longer than the first length, m2 and n2 are real numbers, and m2 is greater than n2, and m2 and n2 are selected in view of the first and second amount of power required to set a memory cell to logic 0 or logic 1;
• wherein the write circuit is further to write the skewed data into the memory, using less power than writing the data into memory.