Bit-line defect detection using unsatisfied parity code checks
AssigneeSeagate Technology LLC
InventorsAbdelHakim S. Alhussien, Erich F. Haratsch, Earl T. Cohen
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Abstract
An apparatus having a device and a circuit is disclosed. The device has a plurality of bit-lines and is configured to store a codeword. The circuit is configured to (i) receive the codeword from the device, (ii) generate a syndrome by performing a portion less than all of an iterative decoding procedure on the codeword and (iii) generate a map of defects according to the syndrome. Each of a plurality of bits in the map corresponds to a respective one of the bit-lines.
Claims20
An apparatus comprising:
- an interface configured to process a plurality of read/write operations to/from a memory, wherein a plurality of bit-lines in the memory are used to access each of at least two codewords;
- and
- a control circuit configured to (i) generate a syndrome during a decode of a first of the at least two codewords, (ii) update a map of defects in the memory according to the syndrome, wherein each of a plurality of bits in the map of defects corresponds to a respective one of the plurality of bit-lines in the memory, and (iii) decode a second of the at least two codewords in response to the map of defects.
A method for bit-line defect detection using unsatisfied parity code checks, comprising the steps of:
- receiving at least two codewords at a circuit from a memory, wherein a plurality of bit-lines in the memory are used to access each of the at least two codewords;
- generating a syndrome during a decode of a first of the at least two codewords;
- updating a map of defects in the memory according to the syndrome, wherein each of a plurality of bits in the map of defects corresponds to a respective one of the plurality of bit-lines of the memory;
- and
- decoding a second of the at least two codewords in response to the map of defects.
An apparatus comprising:
- a memory configured to store data, wherein a plurality of bit-lines in the memory are used to access each of at least two codewords from among the data;
- and
- a controller configured to (i) process a plurality of input/output requests to read/write to/from the memory, (ii) receive the at least two codewords from the memory, (iii) generate a syndrome during a decode of a first of the at least two codewords, (iv) update a map of defects in the memory according to the syndrome, wherein each of a plurality of bits in the map of defects corresponds to a respective one of the plurality of bit-lines in the memory, and (v) decode a second of the at least two codewords in response to the map of defects.
Dependencies are inferred from the claim text.