Machine check summary register

A method comprising:

• receiving error data in a register of a plurality of registers associated with at least one processor, wherein the plurality of registers include a control register to control error reporting for machine check errors produced by a particular hardware unit or group of hardware units, an address register to contain the address of the code or data memory location that produced a particular machine check error, a miscellaneous register to contain additional information describing the machine check error to support software recovery of uncorrected errors, a status register to contain information related to a machine check error if its valid flag is set;
• setting a location in a summary register to indicate a presence of the error data in one of the plurality of registers, the summary register having a plurality of settable locations each corresponding to the plurality of registers;
• in response to a notification of an error, accessing the summary register to identify the register of the plurality of registers that received the error data;
• and
• based at least in part on the accessing the summary register, reading the at least one register that received the error data.

A system comprising:

• at least one processor core;
• a plurality of register banks associated with the at least one processor core to receive error data, wherein each of the plurality of register banks includes a control register to control error reporting for machine check errors produced by a particular hardware unit or group of hardware units, an address register to contain the address of the code or data memory location that produced a particular machine check error, a miscellaneous register to contain additional information describing the machine check error to support software recovery of uncorrected errors, a status register to contain information related to a machine check error if its valid flag is set;
• a summary register having a plurality of indicators corresponding to the plurality of register banks, a respective indicator of the plurality of indicators to indicate presence of error data in a corresponding register bank;
• and
• a register to provide information about a machine check architecture of the at least one processor core.