Reliable, low latency hardware and software inter-process communication channel for safety critical system
AssigneeArtesyn Embedded Computing, Inc.
InventorsPasi Jukka Petteri Vaananen, Martin Peter John Cornes
Life of this patent
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Abstract
A fault-tolerant failsafe computer system including an inter-processor communication channel includes a transmission control module that encodes a first data packet and communicates a first encoded copy of the first data packet and a second encoded copy of the first data packet. The system also includes a receiver control module that i) receives a first encoded copy of a second data packet and a second encoded copy of the second data packet and ii) decodes the first encoded copy and the second encoded copy. The system further includes a de-duplication module that receives a plurality of data packets and communicates at least one unique data packet of the plurality of data packets.
Claims28
A fault-tolerant failsafe computer system including an inter-processor communication channel comprising:
- a multiplexer that receives a plurality of incoming data packets from a plurality of components of the fault-tolerant failsafe computer system and selectively communicates a first data packet;
- a transmission control module receiving the first data packet and encodes the first data packet and communicates a first encoded copy of the first data packet and a second encoded copy of the first data packet;
- a receiver control module that i) receives a first encoded copy of a second data packet and a second encoded copy of the second data packet and ii) decodes the first encoded copy and the second encoded copy;
- a de-duplication module that receives a plurality of data packets from the receiver control module and communicates at least one unique data packet of the plurality of data packets;
- and
- a de-multiplexer that receives the at least one unique data date packet from the de-duplication module and selectively communicates the at least one unique data packet to the plurality of components of the fault-tolerant failsafe computer system.
A method for inter-processor communication comprising:
- encoding a first data packet;
- communicating a first encoded copy of the first data packet and a second encoded copy of the first data packet directly from one of a first or second computer processor to the other of the first or second computer processor;
- receiving at the one of the first or second computer processor a first encoded copy of a second data packet and a second encoded copy of the second data packet from the other of the first or second computer processor;
- decoding the first encoded copy and the second encoded copy of the second data packet;
- receiving the first decoded copy of the second data packet and the second decoded copy of the second data packet;
- and
- communicating at least one unique data packet of the first decoded copy of a second data packet and a second decoded copy of the second data packet.
A fault-tolerant failsafe computer system comprising:
- an inter-processor communication channel for direct communication between a first computer processor and a second computer processor, including:
- a transmission control module that encodes a first data packet and communicates a first encoded copy of the first data packet and a second encoded copy of the first data packet, wherein the first encoded copy of the first data packet and the second encoded copy of the first data packet are communicated directly from one of the first computer processor or the second computer processor to the other of the first computer processor or the second computer processor;
- a receiver control module that i) receives a first encoded copy of a second data packet and a second encoded copy of the second data packet from the other of the first computer processor or the second computer processor and ii) decodes the first encoded copy and the second encoded copy;
- and
- a de-duplication module that receives a plurality of data packets from the receiver control module and communicates at least one unique data packet of the plurality of data packets.
Dependencies are inferred from the claim text.