Back to results
US 9,317,353 B2Granted
Method, apparatus and system for performing voltage margining
AssigneeIntel Corporation
InventorSanjay R. Ravi
Life of this patent
Estimating the term…
Abstract
In one embodiment, a receiver is coupled to a transmitter via an interconnect. The receiver includes a voltage margining circuit to receive non-deterministic data transmitted by the transmitter via a multi-level signaling scheme and to generate a bit error report including bit error information obtained at a plurality of margining levels. Other embodiments are described and claimed.
Claims29
An apparatus comprising:
- a parallel sampler circuit to receive a plurality of signals from an interconnect and to receive a plurality of reference voltage levels from a reference level generator, at least two of the plurality of signals received at opposite polarity levels and a third of the plurality of signals received at a midpoint value between the opposite polarity levels, the parallel sampler circuit to indicate when a bit error occurs for a sample of the plurality of signals, wherein the parallel sampler circuit comprises:
- a plurality of data samplers each to receive a selected pair of a first signal, a second signal, and a third signal of the plurality of signals received from the interconnect, and to output a corresponding value based on a comparison of the selected pair;
- and
- an error collection circuit coupled to the parallel sampler circuit and including one or more error counters to maintain a count of samples having a bit error and to communicate a report of the count of samples maintained for a voltage margining process performed on non-deterministic data.
1 more element
An apparatus comprising:
- a plurality of data samplers each to receive a selected pair of a first signal, a second signal, and a third signal received via an interconnect, and to output a corresponding value based on a comparison of the selected pair;
- a plurality of margin samplers each to receive a selected one of the first, second and third signals and a selected one of a first reference voltage, a second reference voltage, and a third reference voltage, and to output a corresponding margining value based on a comparison of the selected first, second or third signal and the selected first, second, or third reference voltage;
- and
- a plurality of logic circuits each coupled to one of the plurality of data samplers and one of the plurality of margin samplers and to output an error value for a selected pair based on the corresponding value from the corresponding data sampler and the corresponding margining value from the corresponding margin sampler.
1 more element
A method comprising:
- receiving a plurality of signals in a receiver logic of an integrated circuit (IC) via an interconnect;
- comparing a selected pair of the plurality of signals in each of a plurality of data samplers, and comparing a selected signal of the plurality of signals to a selected reference voltage level in each of a plurality of margining samplers;
- and
- updating a first count value in a first error counter based on a comparison of a first output of a first data sampler of the plurality of data samplers with each of a first margining output of a first margining sampler of the plurality of margining samplers and a second margining output of a second margining sampler of the plurality of margining samplers.
1 more element
A system comprising:
- a transmitter to transmit data;
- and
- a receiver coupled to the transmitter via an interconnect, the receiver including a voltage margining circuit to receive non-deterministic data transmitted by the transmitter via a multi-level signaling scheme and to generate a bit error report including bit error information obtained at a plurality of margining levels, wherein the voltage margining circuit comprises:
- a parallel sampler circuit to receive the non-deterministic data as a plurality of signals including a first signal, a second signal and a third signal, the parallel sampler circuit comprising:
- a plurality of data samplers each to receive a selected pair of the first signal, the second signal, and the third signal, and to output a corresponding value based on a comparison of the selected pair.
2 more elements
Dependencies are inferred from the claim text.