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US 9,317,342 B2Granted
Characterization of within-die variations of many-core processors
AssigneeIntel Corporation
InventorSaurabh Dighe
Life of this patent
Estimating the term…
Abstract
A system and method for operating a many-core processor including resilient cores may include determining a frequency variation map for the many-core processor and scheduling execution of a plurality of tasks on respective resilient cores of the many-core processor in accordance to the frequency variation map.
Claims20
A method for operating a many-core processor including resilient cores, comprising:
- determining a frequency variation map for the many-core processor if there is an upgrade to a software application;
- and
- scheduling execution of a plurality of tasks on respective resilient cores from the resilient cores of the many-core processor in accordance to the frequency variation map,
- wherein the determining of the frequency variation map includes:
- dynamically increasing a clock frequency at which the resilient cores execute instructions;
- executing the instructions on the resilient cores;
- monitoring to determine at which clock frequency an error occurs at each resilient core from the resilient cores;
- and
- constructing the frequency variation map based on a maximum tolerable frequency/voltage ratio for each resilient core from the resilient cores.
6 more elements
A many-core processor, comprising:
- resilient cores;
- and
- a storage for storing a frequency variation map if there is an upgrade to a software application,
- wherein a plurality of tasks is scheduled to execute on respective resilient cores from the resilient cores of the many-core processor in accordance to the frequency variation map, and
- wherein the frequency variation map is determined by:
- dynamically increasing a clock frequency at which the resilient cores execute instructions;
- executing the instructions on the resilient cores;
- monitoring to determine at which clock frequency an error occurs at each resilient core from the resilient cores;
- and
- constructing the frequency variation map based on a maximum tolerable frequency/voltage ratio for each resilient core from the resilient cores.
7 more elements
A system comprising:
- a many-core processor including resilient cores;
- and
- a memory accessible by each resilient core from of the resilient cores for storing a frequency variation map if there is an upgrade to a software application,
- wherein a plurality of tasks is scheduled to execute on respective resilient cores from the resilient cores of the many-core processor in accordance to the frequency variation map, and
- wherein the frequency variation map is determined by:
- dynamically increasing a clock frequency at which the resilient cores execute instructions;
- executing the instructions on the resilient cores;
- monitoring to determine at which clock frequency an error occurs at each resilient core from the resilient cores;
- and
- constructing the frequency variation map based on a maximum tolerable frequency/voltage ratio for each resilient core from the resilient cores.
7 more elements
Dependencies are inferred from the claim text.