Interactive scheduling of an application on a multi-core target processor from a co-simulation design environment

A method for interactively varying scheduling of a multi-threaded application, the method comprising:

• interacting with a co-simulation design environment, the co-simulation design environment for co-simulating a model such that a first component of the model is executed on a host device as part of the co-simulating and a second component of the model is executed on a target processor having a plurality of processor cores as part of the co-simulating;
• using an interface to communicate with the target processor;
• allocating execution of the second component to two or more of the plurality of processor cores of the target processor using the interface;
• receiving an interactive instruction from the co-simulation design environment on the host device, the interactive instruction to alter allocation of at least a portion of the execution of the second component;
• receiving execution data regarding the second component executing on the one or more of the plurality of processor cores of the target processor, the receiving occurring in the co-simulation design environment via the interface;
• and
• altering, via the interface, allocation of the at least a portion of the execution of the second component based on the received execution data on the two or more of the plurality of processor cores, the allocating and altering occurring without re-generating, re-compiling or re-running code for the model.

A system for interactively varying scheduling of a multi-threaded application, comprising:

• a memory storing allocation information;
• and
• a processor interacting with the memory and using the allocation information to:
• interact with an interface in a co-simulation design environment, the co-simulation design environment for co-simulating a model such that a first component of the model is executed on a host device as part of the co-simulating and a second component of the model is executed on a target processor having a plurality of processor cores as part of the co-simulating;
• communicate with the target processor;
• allocate execution of the second component to one or more of the plurality of processor cores of the target processor using the interface, the allocating occurring without re-generating, re-compiling or re-running code for the graphical model;
• receive an interactive instruction from the co-simulation design environment on the host device, the interactive instruction to alter allocation of at least a portion of the execution of the second component;
• receive execution data regarding the second component executing on the plurality of processor cores of the target processor, the receiving occurring in the co-simulation design environment via the interface;
• and
• alter, via the interface, allocation of the at least a portion of the execution of the second component based on the received data, the allocating and altering occurring without re-generating, re-compiling or re-running code for the model.