Concurrent multiple instruction issue of non-pipelined instructions using non-pipelined operation resources in another processing core

A method of executing instructions in a processing unit of a type including first and second processing cores disposed on an integrated circuit device, wherein the first processing core includes a first execution unit that includes a first non-pipelined execution logic circuit, the first non-pipelined execution logic circuit configured to execute at least one non-pipelined instruction, and wherein the second processing core includes a second execution unit that includes a second non-pipelined execution logic circuit, the second non-pipelined execution logic circuit configured to execute the at least one non-pipelined instruction, the method comprising:

• in the second processing core, issuing a first non-pipelined instruction to the first non-pipelined execution logic circuit in the first processing core using a multiplexing logic circuit coupling together the first and second execution units and configured to receive a plurality of non-pipelined instructions issued to each of the first and second execution units and route the plurality of non-pipelined instructions to the first non-pipelined execution logic circuit for execution thereby;
• and
• in the second processing core, issuing a second non-pipelined instruction to the second non-pipelined execution logic circuit in the second processing core.