Establishing a branch target instruction cache (BTIC) entry for subroutine returns to reduce execution pipeline bubbles, and related systems, methods, and computer-readable media

A pipeline bubble reduction circuit, comprising:

• a subroutine call detection circuit configured to detect a subroutine call instruction in an execution pipeline;
• and
• a branch target instruction cache (BTIC) entry establishing circuit configured to, in response to the subroutine call detection circuit detecting the subroutine call instruction:
• write at least one sequential instruction fetched sequential to the subroutine call instruction as a branch target instruction in a BTIC entry for a subroutine return instruction;
• calculate a next instruction fetch address;
• and
• write the next instruction fetch address into a next instruction fetch address field in the BTIC entry for the subroutine return instruction.

A non-transitory computer-readable medium having stored thereon computer-executable instructions to cause a processor to implement a method of establishing a branch target instruction cache (BTIC) entry for a subroutine return instruction in an execution pipeline to reduce an occurrence of a pipeline bubble, the method comprising:

• detecting a subroutine call instruction in an execution pipeline;
• and
• in response to detecting the subroutine call instruction, establishing a BTIC entry for a subroutine return instruction by:
• writing at least one sequential instruction fetched sequential to the subroutine call instruction as a branch target instruction in the BTIC entry for the subroutine return instruction;
• calculating a next instruction fetch address;
• and
• writing the next instruction fetch address into a next instruction fetch address field in the BTIC entry for the subroutine return instruction.