Multi-core microprocessor that performs x86 ISA and ARM ISA machine language program instructions by hardware translation into microinstructions executed by common execution pipeline

A method for operating a microprocessor having a plurality of processing cores, each of the plurality of processing cores having an indicator that indicates either the x86 instruction set architecture (ISA) or the Advanced RISC Machines (ARM) ISA, the method comprising:

• for each of the plurality of processing cores:
• determining which of the x86 ISA and the ARM ISA the indicator indicates;
• translating machine language instructions according to the x86 ISA into microinstructions when the indicator indicates the x86 ISA and translating machine language instructions according to the ARM ISA into microinstructions when the indicator indicates the ARM ISA, wherein the microinstructions are defined by a microinstruction set of the microprocessor and are encoded in a distinct manner from the manner in which the instructions defined by the instruction sets of the x86 ISA and ARM ISA are encoded, wherein said translating is performed by a hardware instruction translator of the microprocessor,
• executing the microinstructions to generate results defined by the x86 ISA when the indicator indicates the x86 ISA and executing the microinstructions to generate results defined by the ARM ISA when the indicator indicates the ARM ISA, wherein said executing is performed by an execution pipeline of the microprocessor coupled to the hardware instruction translator,
• caching, in an instruction cache, the x86 ISA and ARM ISA instructions and providing then directly to a hardware instruction translator that performs said translating;
• and
• wherein said translating comprises:
• extracting x86 ISA and ARM ISA instructions from the instruction cache;
• pre-decoding instruction bytes as x86 instruction bytes or ARM instruction bytes;
• and
• indicating each instruction byte as a start byte, an end byte, and/or a valid byte of an ISA instruction;
• translating pre-decoded x86 instructions by an x86 simple instruction translator;
• translating pre-decoded ARM instructions by an ARM simple instruction translator;
• and
• translating a subset of x86 instructions and a subset of ARM instructions by a complex instruction translator.

A computer program product encoded in at least one non-transitory computer readable storage medium for use with a computing device, the computer program product comprising:

• computer readable program code embodied in said medium, for specifying a microprocessor, the computer readable program code comprising:
• program code for specifying a plurality of processing cores, each of the processing cores comprising:
• a hardware instruction translator, that translates instructions of x86 instruction set architecture (ISA) machine language programs and Advanced RISC Machines (ARM) ISA machine language programs into microinstructions defined by a microinstruction set of the microprocessor, wherein the microinstructions are encoded in a distinct manner from the manner in which the instructions defined by the instruction sets of the x86 ISA and ARM ISA are encoded;
• an execution pipeline, coupled to the hardware instruction translator, wherein the execution pipeline executes the microinstructions to generate results defined by the x86 ISA and ARM ISA instructions;
• an instruction cache, that holds the x86 ISA and ARM ISA instructions and provides them directly to the hardware instruction translator;
• and
• wherein the hardware translator comprises:
• an instruction formatter configured to extract x86 ISA and ARM ISA instructions from the instruction cache, to pre-decode instruction bytes as x86 instruction bytes or ARM instruction bytes, and to indicate each instruction be as a start byte, an end byte, and/or a valid byte of an ISA instruction;
• a simple instruction translator including an x86 simple instruction translator to translate pre-decoded x86 instructions from the instruction formatter and an ARM simple instruction translator to translate pre-decoded ARM instructions from the instruction formatter;
• and
• a complex instruction translator to translate a subset of x86 instructions and a subset of ARM instructions.