Apparatus and method for implementing instruction support for the camellia cipher algorithm

A processor, comprising:

• an instruction fetch unit configured to issue instructions for execution, wherein the instructions are programmer-selectable from a defined instruction set architecture (ISA);
• an execution unit configured to execute at least some of the instructions defined within the ISA;
• and
• a cryptographic unit configured to receive particular instructions for execution from the instruction fetch unit, wherein the cryptographic unit includes a plurality of sub-units, wherein the particular instructions include one or more Camellia instructions defined within said ISA, wherein each of the one or more Camellia instructions includes opcode bits specifying a particular Camellia operation and is executable by a corresponding sub-unit of the plurality of sub-units to implement a portion of a Camellia cipher that is compliant with Internet Engineering Task Force (IETF) Request For Comments (RFC) 3713), wherein the portion of the Camellia cipher that is implemented responsive to execution of a given Camellia instruction is dependent upon an opcode encoded in the opcode bits of the given Camellia instruction;
• wherein in response to executing a Camellia F( )-operation instruction of the one or more Camellia instructions, a given sub-unit of the plurality of sub-units is configured to perform a sequence of operations upon a data input operand and a subkey operand, wherein the sequence of operations includes a plurality of Boolean operations, a plurality of shift operations, and a plurality of substitution operations as defined by the Camellia cipher, wherein the data input operand is dependent upon a previous execution of a given Camellia operation, and wherein the subkey operand corresponds to a given one of a plurality of subkeys generated by expanding an initial key.